diff options
Diffstat (limited to 'gas/doc')
-rw-r--r-- | gas/doc/c-bpf.texi | 898 | ||||
-rw-r--r-- | gas/doc/c-i386.texi | 10 | ||||
-rw-r--r-- | gas/doc/local.mk | 2 |
3 files changed, 614 insertions, 296 deletions
diff --git a/gas/doc/c-bpf.texi b/gas/doc/c-bpf.texi index 0756796..6b43c77 100644 --- a/gas/doc/c-bpf.texi +++ b/gas/doc/c-bpf.texi @@ -15,15 +15,15 @@ @cindex BPF support @menu -* BPF Options:: Options -* BPF Syntax:: Syntax -* BPF Directives:: Machine Directives -* BPF Opcodes:: Opcodes -* BPF Pseudo-C Syntax:: Alternative Pseudo-C Assembly Syntax +* BPF Options:: BPF specific command-line options. +* BPF Special Characters:: Comments and statements. +* BPF Registers:: Register names. +* BPF Directives:: Machine directives. +* BPF Instructions:: Machine instructions. @end menu @node BPF Options -@section Options +@section BPF Options @cindex BPF options (none) @cindex options for BPF (none) @@ -38,76 +38,85 @@ This option specifies that the assembler should emit big-endian eBPF. @item -EL This option specifies that the assembler should emit little-endian eBPF. + +@cindex @option{-mdialect} command-line options, BPF +@item -mdialect=@var{dialect} +This option specifies the assembly language dialect to recognize while +assembling. The assembler supports @option{normal} and +@option{pseudoc}. + +@cindex @option{-misa-spec} command-line options, BPF +@item -misa-spec=@var{spec} +This option specifies the version of the BPF instruction set to use +when assembling. The BPF ISA versions supported are @option{v1} @option{v2}, @option{v3} and @option{v4}. + +The value @option{xbpf} can be specified to recognize extra +instructions that are used by GCC for testing purposes. But beware +this is not valid BPF. + +@cindex @option{-mno-relax} command-line options, BPF +@item -mno-relax +This option tells the assembler to not relax instructions. @end table Note that if no endianness option is specified in the command line, the host endianness is used. @c man end -@node BPF Syntax -@section Syntax -@menu -* BPF-Chars:: Special Characters -* BPF-Regs:: Register Names -* BPF-Pseudo-Maps:: Pseudo map fds -@end menu - -@node BPF-Chars -@subsection Special Characters +@node BPF Special Characters +@section BPF Special Characters @cindex line comment character, BPF @cindex BPF line comment character -The presence of a @samp{;} on a line indicates the start of a comment -that extends to the end of the current line. If a @samp{#} appears as -the first character of a line, the whole line is treated as a comment. +The presence of a @samp{;} or a @samp{#} on a line indicates the start +of a comment that extends to the end of the current line. @cindex statement separator, BPF Statements and assembly directives are separated by newlines. -@node BPF-Regs -@subsection Register Names +@node BPF Registers +@section BPF Registers @cindex BPF register names @cindex register names, BPF The eBPF processor provides ten general-purpose 64-bit registers, which are read-write, and a read-only frame pointer register: +@noindent +In normal syntax: + @table @samp @item %r0 .. %r9 General-purpose registers. @item %r10 -Frame pointer register. +@itemx %fp +Read-only frame pointer register. @end table -Some registers have additional names, to reflect their role in the -eBPF ABI: +All BPF registers are 64-bit long. However, in the Pseudo-C syntax +registers can be referred using different names, which actually +reflect the kind of instruction they appear on: + +@noindent +In pseudoc syntax: @table @samp -@item %a -This is @samp{%r0}. -@item %ctx -This is @samp{%r6}. -@item %fp -This is @samp{%r10}. +@item r0..r9 +General-purpose register in an instruction that operates on its value +as if it was a 64-bit value. +@item w0..w9 +General-purpose register in an instruction that operates on its value +as if it was a 32-bit value. +@item r10 +Read-only frame pointer register. @end table -@node BPF-Pseudo-Maps -@subsection Pseudo Maps - -@cindex pseudo map fd, BPF -The @samp{LDDW} instruction can take a literal pseudo map file -descriptor as its second argument. This uses the syntax -@samp{%map_fd(N)} where @samp{N} is a signed number. - -For example, to load the address of the pseudo map with file -descriptor @samp{2} in register @samp{r1} we would do: - -@smallexample - lddw %r1, %map_fd(2) -@end smallexample +@noindent +Note that in the Pseudo-C syntax register names are not preceded by +@code{%} characters. @node BPF Directives -@section Machine Directives +@section BPF Directives @cindex machine directives, BPF @@ -128,8 +137,8 @@ The @code{.word} directive produces a 32 bit value. The @code{.dword} directive produces a 64 bit value. @end table -@node BPF Opcodes -@section Opcodes +@node BPF Instructions +@section BPF Instructions @cindex BPF opcodes @cindex opcodes for BPF @@ -137,10 +146,10 @@ In the instruction descriptions below the following field descriptors are used: @table @code -@item %d -Destination general-purpose register whose role is to be destination -of an operation. -@item %s +@item rd +Destination general-purpose register whose role is to be the +destination of an operation. +@item rs Source general-purpose register whose role is to be the source of an operation. @item disp16 @@ -150,104 +159,284 @@ minus one. 32-bit signed PC-relative offset, measured in number of 64-bit words, minus one. @item offset16 -Signed 16-bit immediate. +Signed 16-bit immediate representing an offset in bytes. +@item disp16 +Signed 16-bit immediate representing a displacement to a target, +measured in number of 64-bit words @emph{minus one}. +@item disp32 +Signed 32-bit immediate representing a displacement to a target, +measured in number of 64-bit words @emph{minus one}. @item imm32 Signed 32-bit immediate. @item imm64 Signed 64-bit immediate. @end table -@subsubsection Arithmetic instructions +@subsection Arithmetic instructions The destination register in these instructions act like an accumulator. +Note that in pseudoc syntax these instructions should use @code{r} +registers. + @table @code -@item add %d, (%s|imm32) +@item add rd, rs +@itemx add rd, imm32 +@itemx rd += rs +@itemx rd += imm32 64-bit arithmetic addition. -@item sub %d, (%s|imm32) + +@item sub rd, rs +@itemx sub rd, rs +@itemx rd -= rs +@itemx rd -= imm32 64-bit arithmetic subtraction. -@item mul %d, (%s|imm32) + +@item mul rd, rs +@itemx mul rd, imm32 +@itemx rd *= rs +@itemx rd *= imm32 64-bit arithmetic multiplication. -@item div %d, (%s|imm32) + +@item div rd, rs +@itemx div rd, imm32 +@itemx rd /= rs +@itemx rd /= imm32 64-bit arithmetic integer division. -@item mod %d, (%s|imm32) + +@item mod rd, rs +@itemx mod rd, imm32 +@itemx rd %= rs +@itemx rd %= imm32 64-bit integer remainder. -@item and %d, (%s|imm32) + +@item and rd, rs +@itemx and rd, imm32 +@itemx rd &= rs +@itemx rd &= imm32 64-bit bit-wise ``and'' operation. -@item or %d, (%s|imm32) + +@item or rd, rs +@itemx or rd, imm32 +@itemx rd |= rs +@itemx rd |= imm32 64-bit bit-wise ``or'' operation. -@item xor %d, (%s|imm32) + +@item xor rd, imm32 +@itemx xor rd, rs +@itemx rd ^= rs +@itemx rd ^= imm32 64-bit bit-wise exclusive-or operation. -@item lsh %d, (%s|imm32) -64-bit left shift, by @code{%s} or @code{imm32} bits. -@item rsh %d, (%s|imm32) -64-bit right logical shift, by @code{%s} or @code{imm32} bits. -@item arsh %d, (%s|imm32) -64-bit right arithmetic shift, by @code{%s} or @code{imm32} bits. -@item neg %d + +@item lsh rd, rs +@itemx ldh rd, imm32 +@itemx rd <<= rs +@itemx rd <<= imm32 +64-bit left shift, by @code{rs} or @code{imm32} bits. + +@item rsh %d, %s +@itemx rsh rd, imm32 +@itemx rd >>= rs +@itemx rd >>= imm32 +64-bit right logical shift, by @code{rs} or @code{imm32} bits. + +@item arsh rd, rs +@itemx arsh rd, imm32 +@itemx rd s>>= rs +@itemx rd s>>= imm32 +64-bit right arithmetic shift, by @code{rs} or @code{imm32} bits. + +@item neg rd +@itemx neg rd, imm32 +@itemx rd = - rd +@itemx rd = - imm32 64-bit arithmetic negation. -@item mov %d, (%s|imm32) -Move the 64-bit value of @code{%s} in @code{%d}, or load @code{imm32} -in @code{%d}. + +Note that in the @code{rd = - imm32} syntax there must be at least +one white space between @code{-} and @code{imm32}. Otherwise the +instruction is parsed as a @code{mov rd, imm32} instruction with a +negative 32-bit immediate. This is a consequence of a syntactic +ambiguity in the pseudoc syntax. + +@item mov rd, rs +@itemx mov rd, imm32 +@itemx rd = rs +@itemx rd = imm32 +Move the 64-bit value of @code{rs} in @code{rd}, or load @code{imm32} +in @code{rd}. + +@item movs rd, rs, 8 +@itemx rd = (s8) rs +Move the sign-extended 8-bit value in @code{rs} to @code{rd}. + +@item movs rd, rs, 16 +@itemx rd = (s16) rs +Move the sign-extended 16-bit value in @code{rs} to @code{rd}. + +@item movs rd, rs, 32 +@itemx rd = (s32) rs +Move the sign-extended 32-bit value in @code{rs} to @code{rd}. @end table -@subsubsection 32-bit arithmetic instructions +@subsection 32-bit arithmetic instructions The destination register in these instructions act as an accumulator. +Note that in pseudoc syntax these instructions should use @code{w} +registers. It is not allowed to mix @code{w} and @code{r} registers +in the same instruction. + @table @code -@item add32 %d, (%s|imm32) +@item add32 rd, rs +@itemx add32 rd, imm32 +@itemx rd += rs +@itemx rd += imm32 32-bit arithmetic addition. -@item sub32 %d, (%s|imm32) + +@item sub32 rd, rs +@itemx sub32 rd, imm32 +@itemx rd -= rs +@itemx rd += imm32 32-bit arithmetic subtraction. -@item mul32 %d, (%s|imm32) + +@item mul32 rd, rs +@itemx mul32 rd, imm32 +@itemx rd *= rs +@itemx rd *= imm32 32-bit arithmetic multiplication. -@item div32 %d, (%s|imm32) + +@item div32 rd, rs +@itemx div32 rd, imm32 +@itemx rd /= rs +@itemx rd /= imm32 32-bit arithmetic integer division. -@item mod32 %d, (%s|imm32) + +@item mod32 rd, rs +@itemx mod32 rd, imm32 +@itemx rd %= rs +@itemx rd %= imm32 32-bit integer remainder. -@item and32 %d, (%s|imm32) + +@item and32 rd, rs +@itemx and32 rd, imm32 +@itemx rd &= rs +@itemx rd &= imm32 32-bit bit-wise ``and'' operation. -@item or32 %d, (%s|imm32) + +@item or32 rd, rs +@itemx or32 rd, imm32 +@itemx rd |= rs +@itemx rd |= imm32 32-bit bit-wise ``or'' operation. -@item xor32 %d, (%s|imm32) + +@item xor32 rd, rs +@itemx xor32 rd, imm32 +@itemx rd ^= rs +@itemx rd ^= imm32 32-bit bit-wise exclusive-or operation. -@item lsh32 %d, (%s|imm32) -32-bit left shift, by @code{%s} or @code{imm32} bits. -@item rsh32 %d, (%s|imm32) -32-bit right logical shift, by @code{%s} or @code{imm32} bits. -@item arsh32 %d, (%s|imm32) -32-bit right arithmetic shift, by @code{%s} or @code{imm32} bits. -@item neg32 %d + +@item lsh32 rd, rs +@itemx lsh32 rd, imm32 +@itemx rd <<= rs +@itemx rd <<= imm32 +32-bit left shift, by @code{rs} or @code{imm32} bits. + +@item rsh32 rd, rs +@itemx rsh32 rd, imm32 +@itemx rd >>= rs +@itemx rd >>= imm32 +32-bit right logical shift, by @code{rs} or @code{imm32} bits. + +@item arsh32 rd, rs +@itemx arsh32 rd, imm32 +@itemx rd s>>= rs +@itemx rd s>>= imm32 +32-bit right arithmetic shift, by @code{rs} or @code{imm32} bits. + +@item neg32 rd +@itemx neg32 rd, imm32 +@itemx rd = - rd +@itemx rd = - imm32 32-bit arithmetic negation. -@item mov32 %d, (%s|imm32) -Move the 32-bit value of @code{%s} in @code{%d}, or load @code{imm32} -in @code{%d}. + +Note that in the @code{rd = - imm32} syntax there must be at least +one white space between @code{-} and @code{imm32}. Otherwise the +instruction is parsed as a @code{mov32 rd, imm32} instruction with a +negative 32-bit immediate. This is a consequence of a syntactic +ambiguity in the pseudoc syntax. + +@item mov32 rd, rs +@itemx mov32 rd, imm32 +@itemx rd = rs +@itemx rd = imm32 +Move the 32-bit value of @code{rs} in @code{rd}, or load @code{imm32} +in @code{rd}. + +@item mov32s rd, rs, 8 +@itemx rd = (s8) rs +Move the sign-extended 8-bit value in @code{rs} to @code{rd}. + +@item mov32s rd, rs, 16 +@itemx rd = (s16) rs +Move the sign-extended 16-bit value in @code{rs} to @code{rd}. + +@item mov32s rd, rs, 32 +@itemx rd = (s32) rs +Move the sign-extended 32-bit value in @code{rs} to @code{rd}. +@end table + +@subsection Endianness conversion instructions + +@table @code +@item endle rd, 16 +@itemx endle rd, 32 +@itemx endle rd, 64 +@itemx rd = le16 rd +@itemx rd = le32 rd +@itemx rd = le64 rd +Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to +little-endian and store it back in @code{rd}. +@item endbe %d, 16 +@itemx endbe %d, 32 +@itemx endbe %d, 64 +@itemx rd = be16 rd +@itemx rd = be32 rd +@itemx rd = be64 rd +Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to big-endian +and store it back in @code{rd}. @end table -@subsubsection Endianness conversion instructions +@subsection Byte swap instructions @table @code -@item endle %d, (16|32|64) -Convert the 16-bit, 32-bit or 64-bit value in @code{%d} to -little-endian. -@item endbe %d, (16|32|64) -Convert the 16-bit, 32-bit or 64-bit value in @code{%d} to big-endian. +@item bswap rd, 16 +@itemx rd = bswap16 rd +Swap the least-significant 16-bit word in @code{rd} with the +most-significant 16-bit word. + +@item bswap rd, 32 +@itemx rd = bswap32 rd +Swap the least-significant 32-bit word in @code{rd} with the +most-significant 32-bit word. + +@item bswap rd, 64 +@itemx rd = bswap64 rd +Swap the least-significant 64-bit word in @code{rd} with the +most-significant 64-bit word. @end table -@subsubsection 64-bit load and pseudo maps + +@subsection 64-bit load and pseudo maps @table @code -@item lddw %d, imm64 -Load the given signed 64-bit immediate, or pseudo map descriptor, to -the destination register @code{%d}. -@item lddw %d, %map_fd(N) -Load the address of the given pseudo map fd @emph{N} to the -destination register @code{%d}. +@item lddw rd, imm64 +@itemx rd = imm64 ll +Load the given signed 64-bit immediate to the destination register +@code{rd}. @end table -@subsubsection Load instructions for socket filters +@subsection Load instructions for socket filters The following instructions are intended to be used in socket filters, and are therefore not general-purpose: they make assumptions on the @@ -259,29 +448,43 @@ Absolute loads: @table @code @item ldabsdw imm32 +@itemx r0 = *(u64 *) skb[imm32] Absolute 64-bit load. + @item ldabsw imm32 +@itemx r0 = *(u32 *) skb[imm32] Absolute 32-bit load. + @item ldabsh imm32 +@itemx r0 = *(u16 *) skb[imm32] Absolute 16-bit load. + @item ldabsb imm32 +@itemx r0 = *(u8 *) skb[imm32] Absolute 8-bit load. @end table Indirect loads: @table @code -@item ldinddw %s, imm32 +@item ldinddw rs, imm32 +@itemx r0 = *(u64 *) skb[rs + imm32] Indirect 64-bit load. -@item ldindw %s, imm32 + +@item ldindw rs, imm32 +@itemx r0 = *(u32 *) skb[rs + imm32] Indirect 32-bit load. -@item ldindh %s, imm32 + +@item ldindh rs, imm32 +@itemx r0 = *(u16 *) skb[rs + imm32] Indirect 16-bit load. + @item ldindb %s, imm32 +@itemx r0 = *(u8 *) skb[rs + imm32] Indirect 8-bit load. @end table -@subsubsection Generic load/store instructions +@subsection Generic load/store instructions General-purpose load and store instructions are provided for several word sizes. @@ -289,43 +492,84 @@ word sizes. Load to register instructions: @table @code -@item ldxdw %d, [%s+offset16] +@item ldxdw rd, [rs + offset16] +@itemx rd = *(u64 *) (rs + offset16) Generic 64-bit load. -@item ldxw %d, [%s+offset16] + +@item ldxw rd, [rs + offset16] +@itemx rd = *(u32 *) (rs + offset16) Generic 32-bit load. -@item ldxh %d, [%s+offset16] + +@item ldxh rd, [rs + offset16] +@itemx rd = *(u16 *) (rs + offset16) Generic 16-bit load. -@item ldxb %d, [%s+offset16] + +@item ldxb rd, [rs + offset16] +@itemx rd = *(u8 *) (rs + offset16) Generic 8-bit load. @end table +Signed load to register instructions: + +@table @code +@item ldxsdw rd, [rs + offset16] +@itemx rd = *(s64 *) (rs + offset16) +Generic 64-bit signed load. + +@item ldxsw rd, [rs + offset16] +@itemx rd = *(s32 *) (rs + offset16) +Generic 32-bit signed load. + +@item ldxsh rd, [rs + offset16] +@itemx rd = *(s16 *) (rs + offset16) +Generic 16-bit signed load. + +@item ldxsb rd, [rs + offset16] +@itemx rd = *(s8 *) (rs + offset16) +Generic 8-bit signed load. +@end table + Store from register instructions: @table @code -@item stxdw [%d+offset16], %s +@item stxdw [rd + offset16], %s +@itemx *(u64 *) (rd + offset16) Generic 64-bit store. -@item stxw [%d+offset16], %s + +@item stxw [rd + offset16], %s +@itemx *(u32 *) (rd + offset16) Generic 32-bit store. -@item stxh [%d+offset16], %s + +@item stxh [rd + offset16], %s +@itemx *(u16 *) (rd + offset16) Generic 16-bit store. -@item stxb [%d+offset16], %s + +@item stxb [rd + offset16], %s +@itemx *(u8 *) (rd + offset16) Generic 8-bit store. @end table Store from immediates instructions: @table @code -@item stddw [%d+offset16], imm32 +@item stdw [rd + offset16], imm32 +@itemx *(u64 *) (rd + offset16) = imm32 Store immediate as 64-bit. -@item stdw [%d+offset16], imm32 + +@item stw [rd + offset16], imm32 +@itemx *(u32 *) (rd + offset16) = imm32 Store immediate as 32-bit. -@item stdh [%d+offset16], imm32 + +@item sth [rd + offset16], imm32 +@itemx *(u16 *) (rd + offset16) = imm32 Store immediate as 16-bit. -@item stdb [%d+offset16], imm32 + +@item stb [rd + offset16], imm32 +@itemx *(u8 *) (rd + offset16) = imm32 Store immediate as 8-bit. @end table -@subsubsection Jump instructions +@subsection Jump instructions eBPF provides the following compare-and-jump instructions, which compare the values of the two given registers, or the values of a @@ -333,29 +577,78 @@ register and an immediate, and perform a branch in case the comparison holds true. @table @code -@item ja %d,(%s|imm32),disp16 +@item ja disp16 +@itemx goto disp16 Jump-always. -@item jeq %d,(%s|imm32),disp16 + +@item jal disp32 +@itemx gotol disp32 +Jump-always, long range. + +@item jeq rd, rs, disp16 +@itemx jeq rd, imm32, disp16 +@itemx if rd == rs goto disp16 +@itemx if rd == imm32 goto disp16 Jump if equal, unsigned. -@item jgt %d,(%s|imm32),disp16 + +@item jgt rd, rs, disp16 +@itemx jgt rd, imm32, disp16 +@itemx if rd > rs goto disp16 +@itemx if rd > imm32 goto disp16 Jump if greater, unsigned. -@item jge %d,(%s|imm32),disp16 + +@item jge rd, rs, disp16 +@itemx jge rd, imm32, disp16 +@itemx if rd >= rs goto disp16 +@itemx if rd >= imm32 goto disp16 Jump if greater or equal. -@item jlt %d,(%s|imm32),disp16 + +@item jlt rd, rs, disp16 +@itemx jlt rd, imm32, disp16 +@itemx if rd < rs goto disp16 +@itemx if rd < imm32 goto disp16 Jump if lesser. -@item jle %d,(%s|imm32),disp16 + +@item jle rd , rs, disp16 +@itemx jle rd, imm32, disp16 +@itemx if rd <= rs goto disp16 +@itemx if rd <= imm32 goto disp16 Jump if lesser or equal. -@item jset %d,(%s|imm32),disp16 + +@item jset rd, rs, disp16 +@itemx jset rd, imm32, disp16 +@itemx if rd & rs goto disp16 +@itemx if rd & imm32 goto disp16 Jump if signed equal. -@item jne %d,(%s|imm32),disp16 + +@item jne rd, rs, disp16 +@itemx jne rd, imm32, disp16 +@itemx if rd != rs goto disp16 +@itemx if rd != imm32 goto disp16 Jump if not equal. -@item jsgt %d,(%s|imm32),disp16 + +@item jsgt rd, rs, disp16 +@itemx jsgt rd, imm32, disp16 +@itemx if rd s> rs goto disp16 +@itemx if rd s> imm32 goto disp16 Jump if signed greater. -@item jsge %d,(%s|imm32),disp16 + +@item jsge rd, rs, disp16 +@itemx jsge rd, imm32, disp16 +@itemx if rd s>= rd goto disp16 +@itemx if rd s>= imm32 goto disp16 Jump if signed greater or equal. -@item jslt %d,(%s|imm32),disp16 + +@item jslt rd, rs, disp16 +@itemx jslt rd, imm32, disp16 +@itemx if rd s< rs goto disp16 +@itemx if rd s< imm32 goto disp16 Jump if signed lesser. -@item jsle %d,(%s|imm32),disp16 + +@item jsle rd, rs, disp16 +@itemx jsle rd, imm32, disp16 +@itemx if rd s<= rs goto disp16 +@itemx if rd s<= imm32 goto disp16 Jump if signed lesser or equal. @end table @@ -363,7 +656,8 @@ A call instruction is provided in order to perform calls to other eBPF functions, or to external kernel helpers: @table @code -@item call (disp32|imm32) +@item call disp32 +@item call imm32 Jump and link to the offset @emph{disp32}, or to the kernel helper function identified by @emph{imm32}. @end table @@ -375,203 +669,221 @@ Finally: Terminate the eBPF program. @end table -@subsubsection Atomic instructions +@subsection 32-bit jump instructions + +eBPF provides the following compare-and-jump instructions, which +compare the 32-bit values of the two given registers, or the values of +a register and an immediate, and perform a branch in case the +comparison holds true. -Atomic exchange-and-add instructions are provided in two flavors: one -for swapping 64-bit quantities and another for 32-bit quantities. +These instructions are only available in BPF v3 or later. @table @code -@item xadddw [%d+offset16],%s -Exchange-and-add a 64-bit value at the specified location. -@item xaddw [%d+offset16],%s -Exchange-and-add a 32-bit value at the specified location. -@end table +@item jeq32 rd, rs, disp16 +@itemx jeq32 rd, imm32, disp16 +@itemx if rd == rs goto disp16 +@itemx if rd == imm32 goto disp16 +Jump if equal, unsigned. -@node BPF Pseudo-C Syntax -@section BPF Pseudo-C Syntax +@item jgt32 rd, rs, disp16 +@itemx jgt32 rd, imm32, disp16 +@itemx if rd > rs goto disp16 +@itemx if rd > imm32 goto disp16 +Jump if greater, unsigned. -This assembler supports another syntax to denote BPF instructions, -which is an alternative to the normal looking syntax documented above. -This alternatative syntax, which we call @dfn{pseudo-C syntax}, is -supported by the LLVM/clang integrated assembler. +@item jge32 rd, rs, disp16 +@itemx jge32 rd, imm32, disp16 +@itemx if rd >= rs goto disp16 +@itemx if rd >= imm32 goto disp16 +Jump if greater or equal. -This syntax is very unconventional, but we need to support it in order -to support inline assembly in existing BPF programs. +@item jlt32 rd, rs, disp16 +@itemx jlt32 rd, imm32, disp16 +@itemx if rd < rs goto disp16 +@itemx if rd < imm32 goto disp16 +Jump if lesser. -Note that the assembler is able to parse sources in which both -syntaxes coexist: some instructions can use the usual assembly like -syntax, whereas some other instructions in the same file can use the -pseudo-C syntax. +@item jle32 rd , rs, disp16 +@itemx jle32 rd, imm32, disp16 +@itemx if rd <= rs goto disp16 +@itemx if rd <= imm32 goto disp16 +Jump if lesser or equal. -@subsubsection Pseudo-C Register Names +@item jset32 rd, rs, disp16 +@itemx jset32 rd, imm32, disp16 +@itemx if rd & rs goto disp16 +@itemx if rd & imm32 goto disp16 +Jump if signed equal. -All BPF registers are 64-bit long. However, in the Pseudo-C syntax -registers can be referred using different names, which actually -reflect the kind of instruction they appear on: +@item jne32 rd, rs, disp16 +@itemx jne32 rd, imm32, disp16 +@itemx if rd != rs goto disp16 +@itemx if rd != imm32 goto disp16 +Jump if not equal. -@table @samp -@item r0..r9 -General-purpose register in an instruction that operates on its value -as if it was a 64-bit value. -@item w0..w9 -General-purpose register in an instruction that operates on its value -as if it was a 32-bit value. +@item jsgt32 rd, rs, disp16 +@itemx jsgt32 rd, imm32, disp16 +@itemx if rd s> rs goto disp16 +@itemx if rd s> imm32 goto disp16 +Jump if signed greater. + +@item jsge32 rd, rs, disp16 +@itemx jsge32 rd, imm32, disp16 +@itemx if rd s>= rd goto disp16 +@itemx if rd s>= imm32 goto disp16 +Jump if signed greater or equal. + +@item jslt32 rd, rs, disp16 +@itemx jslt32 rd, imm32, disp16 +@itemx if rd s< rs goto disp16 +@itemx if rd s< imm32 goto disp16 +Jump if signed lesser. + +@item jsle32 rd, rs, disp16 +@itemx jsle32 rd, imm32, disp16 +@itemx if rd s<= rs goto disp16 +@itemx if rd s<= imm32 goto disp16 +Jump if signed lesser or equal. @end table -@noindent -Note that in the Pseudo-C syntax register names are not preceded by -@code{%} characters. +@subsection Atomic instructions -@subsubsection Arithmetic instructions +Atomic exchange instructions are provided in two flavors: one for +compare-and-swap, one for unconditional exchange. + +@table @code +@item acmp [rd + offset16], rs +@itemx r0 = cmpxchg_64 (rd + offset16, r0, rs) +Atomic compare-and-swap. Compares value in @code{r0} to value +addressed by @code{rd + offset16}. On match, the value addressed by +@code{rd + offset16} is replaced with the value in @code{rs}. +Regardless, the value that was at @code{rd + offset16} is +zero-extended and loaded into @code{r0}. + +@item axchg [rd + offset16], rs +@itemx rs = xchg_64 (rd + offset16, rs) +Atomic exchange. Atomically exchanges the value in @code{rs} with +the value addressed by @code{rd + offset16}. +@end table -In all the instructions below, the operations are 64-bit or 32-bit -depending on the names used to refer to the registers. For example -@code{r3 += r2} will perform 64-bit addition, whereas @code{w3 += w2} -will perform 32-bit addition. Mixing register prefixes is an error, -for example @code{r3 += w2}. +@noindent +The following instructions provide atomic arithmetic operations. @table @code -@item dst_reg += (imm32|src_reg) -Arithmetic addition. -@item dst_reg -= (imm32|src_reg) -Arithmetic subtraction. -@item dst_reg *= (imm32|src_reg) -Arithmetic multiplication. -@item dst_reg /= (imm32|src_reg) -Arithmetic integer unsigned division. -@item dst_reg %= (imm32|src_reg) -Arithmetic integer unsigned remainder. -@item dst_reg &= (imm32|src_reg) -Bit-wise ``and'' operation. -@item dst_reg |= (imm32|src_reg) -Bit-wise ``or'' operation. -@item dst_reg ^= (imm32|src_reg) -Bit-wise exclusive-or operation. -@item dst_reg <<= (imm32|src_reg) -Left shift, by whatever specified number of bits. -@item dst_reg >>= (imm32|src_reg) -Right logical shift, by whatever specified number of bits. -@item dst_reg s>>= (imm32|src_reg) -Right arithmetic shift, by whatever specified number of bits. -@item dst_reg = (imm32|src_reg) -Move the value in @code{imm32} or @code{src_reg} in @code{dst_reg}. -@item dst_reg = -dst_reg -Arithmetic negation. +@item aadd [rd + offset16], rs +@itemx lock *(u64 *)(rd + offset16) = rs +Atomic add instruction. + +@item aor [rd + offset16], rs +@itemx lock *(u64 *) (rd + offset16) |= rs +Atomic or instruction. + +@item aand [rd + offset16], rs +@itemx lock *(u64 *) (rd + offset16) &= rs +Atomic and instruction. + +@item axor [rd + offset16], rs +@itemx lock *(u64 *) (rd + offset16) ^= rs +Atomic xor instruction. @end table -@subsubsection Endianness conversion instructions +@noindent +The following variants perform fetching before the atomic operation. @table @code -@item dst_reg = le16 src_reg -Convert the 16-bit value in @code{src_reg} to little-endian. -@item dst_reg = le32 src_reg -Convert the 32-bit value in @code{src_reg} to little-endian. -@item dst_reg = le64 src_reg -Convert the 64-bit value in @code{src_reg} to little-endian. -@item dst_reg = be16 src_reg -Convert the 16-bit value in @code{src_reg} to big-endian. -@item dst_reg = be32 src_reg -Convert the 32-bit value in @code{src_reg} to big-endian. -@item dst_reg = be64 src_reg -Convert the 64-bit value in @code{src_reg} to big-endian. +@item afadd [rd + offset16], rs +@itemx rs = atomic_fetch_add ((u64 *)(rd + offset16), rs) +Atomic fetch-and-add instruction. + +@item afor [rd + offset16], rs +@itemx rs = atomic_fetch_or ((u64 *)(rd + offset16), rs) +Atomic fetch-and-or instruction. + +@item afand [rd + offset16], rs +@itemx rs = atomic_fetch_and ((u64 *)(rd + offset16), rs) +Atomic fetch-and-and instruction. + +@item afxor [rd + offset16], rs +@itemx rs = atomic_fetch_xor ((u64 *)(rd + offset16), rs) +Atomic fetch-and-or instruction. @end table -@subsubsection 64-bit load and pseudo maps +The above instructions were introduced in the V3 of the BPF +instruction set. The following instruction is supported for backwards +compatibility: @table @code -@item dst_reg = imm64 ll -Load the given signed 64-bit immediate, or pseudo map descriptor, to -the destination register @code{dst_reg}. +@item xadddw [rd + offset16], rs +Alias to @code{aadd}. @end table -@subsubsection Load instructions for socket filters +@subsection 32-bit atomic instructions + +32-bit atomic exchange instructions are provided in two flavors: one +for compare-and-swap, one for unconditional exchange. @table @code -@item r0 = *(u8 *)skb[imm32] -Absolute 8-bit load. -@item r0 = *(u16 *)skb[imm32] -Absolute 16-bit load. -@item r0 = *(u32 *)skb[imm32] -Absolute 32-bit load. -@item r0 = *(u64 *)skb[imm32] -Absolute 64-bit load. -@item r0 = *(u8 *)skb[src_reg + imm32] -Indirect 8-bit load. -@item r0 = *(u16 *)skb[src_reg + imm32] -Indirect 16-bit load. -@item r0 = *(u32 *)skb[src_reg + imm32] -Indirect 32-bit load. -@item r0 = *(u64 *)skb[src_reg + imm32] -Indirect 64-bit load. +@item acmp32 [rd + offset16], rs +@itemx w0 = cmpxchg32_32 (rd + offset16, w0, ws) +Atomic compare-and-swap. Compares value in @code{w0} to value +addressed by @code{rd + offset16}. On match, the value addressed by +@code{rd + offset16} is replaced with the value in @code{ws}. +Regardless, the value that was at @code{rd + offset16} is +zero-extended and loaded into @code{w0}. + +@item axchg [rd + offset16], rs +@itemx ws = xchg32_32 (rd + offset16, ws) +Atomic exchange. Atomically exchanges the value in @code{ws} with +the value addressed by @code{rd + offset16}. @end table -@subsubsection Generic load/store instructions +@noindent +The following instructions provide 32-bit atomic arithmetic operations. @table @code -@item dst_reg = *(u8 *)(src_reg + offset16) -Generic 8-bit load. -@item dst_reg = *(u16 *)(src_reg + offset16) -Generic 16-bit load. -@item dst_reg = *(u32 *)(src_reg + offset16) -Generic 32-bit load. -@item dst_reg = *(u64 *)(src_reg + offset16) -Generic 64-bit load. -@c XXX stb -@c NO PSEUDOC-SYNTAX -@c XXX sth -@c NO PSEUDOC-SYNTAX -@c XXX stw -@c NO PSEUDOC-SYNTAX -@c XXX stdw -@c NO PSEUDOC-SYNTAX -@item *(u8 *)(dst_reg + offset16) = src_reg -Generic 8-bit store. -@item *(u16 *)(dst_reg + offset16) = src_reg -Generic 16-bit store. -@item *(u32 *)(dst_reg + offset16) = src_reg -Generic 32-bit store. -@item *(u64 *)(dst_reg + offset16) = src_reg -Generic 64-bit store. +@item aadd32 [rd + offset16], rs +@itemx lock *(u32 *)(rd + offset16) = rs +Atomic add instruction. + +@item aor32 [rd + offset16], rs +@itemx lock *(u32 *) (rd + offset16) |= rs +Atomic or instruction. + +@item aand32 [rd + offset16], rs +@itemx lock *(u32 *) (rd + offset16) &= rs +Atomic and instruction. + +@item axor32 [rd + offset16], rs +@itemx lock *(u32 *) (rd + offset16) ^= rs +Atomic xor instruction @end table -@subsubsection Jump instructions +@noindent +The following variants perform fetching before the atomic operation. @table @code -@item goto disp16 -Jump-always. -@item if dst_reg == (imm32|src_reg) goto disp16 -Jump if equal. -@item if dst_reg & (imm32|src_reg) goto disp16 -Jump if signed equal. -@item if dst_reg != (imm32|src_reg) goto disp16 -Jump if not equal. -@item if dst_reg > (imm32|src_reg) goto disp16 -Jump if bigger, unsigned. -@item if dst_reg < (imm32|src_reg) goto disp16 -Jump if smaller, unsigned. -@item if dst_reg >= (imm32|src_reg) goto disp16 -Jump if bigger or equal, unsigned. -@item if dst_reg <= (imm32|src_reg) goto disp16 -Jump if smaller or equal, unsigned. -@item if dst_reg s> (imm32|src_reg) goto disp16 -Jump if bigger, signed. -@item if dst_reg s< (imm32|src_reg) goto disp16 -Jump if smaller, signed. -@item if dst_reg s>= (imm32|src_reg) goto disp16 -Jump if bigger or equal, signed. -@item if dst_reg s<= (imm32|src_reg) goto disp16 -Jump if smaller or equal, signed. -@item call imm32 -Jump and link. -@item exit -Terminate the eBPF program. +@item afadd32 [dr + offset16], rs +@itemx ws = atomic_fetch_add ((u32 *)(rd + offset16), ws) +Atomic fetch-and-add instruction. + +@item afor32 [dr + offset16], rs +@itemx ws = atomic_fetch_or ((u32 *)(rd + offset16), ws) +Atomic fetch-and-or instruction. + +@item afand32 [dr + offset16], rs +@itemx ws = atomic_fetch_and ((u32 *)(rd + offset16), ws) +Atomic fetch-and-and instruction. + +@item afxor32 [dr + offset16], rs +@itemx ws = atomic_fetch_xor ((u32 *)(rd + offset16), ws) +Atomic fetch-and-or instruction @end table -@subsubsection Atomic instructions +The above instructions were introduced in the V3 of the BPF +instruction set. The following instruction is supported for backwards +compatibility: @table @code -@item lock *(u64 *)(dst_reg + offset16) += src_reg -Exchange-and-add a 64-bit value at the specified location. -@item lock *(u32 *)(dst_reg + offset16) += src_reg -Exchange-and-add a 32-bit value at the specified location. +@item xaddw [rd + offset16], rs +Alias to @code{aadd32}. @end table diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 49b6e3b..dd06282 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -207,6 +207,11 @@ accept various extension mnemonics. For example, @code{rao_int}, @code{fred}, @code{lkgs}, +@code{avx_vnni_int16}, +@code{sha512}, +@code{sm3}, +@code{sm4}, +@code{pbndkb}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1635,8 +1640,9 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} -@item @samp{.avx_ne_convert} @tab @samp{.rao_int} -@item @samp{.fred} @tab @samp{.lkgs} +@item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs} +@item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4} +@item @samp{.pbndkb} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/doc/local.mk b/gas/doc/local.mk index de13e3c..c48c711 100644 --- a/gas/doc/local.mk +++ b/gas/doc/local.mk @@ -41,7 +41,7 @@ TEXI2DVI = texi2dvi -I "$(srcdir)/%D%" -I %D% -I "$(srcdir)/../libiberty" \ %D%/asconfig.texi: %D%/$(CONFIG).texi %D%/$(am__dirstamp) $(AM_V_at)rm -f %D%/asconfig.texi - $(AM_V_GEN)cp -p $(srcdir)/%D%/$(CONFIG).texi %D%/asconfig.texi + $(AM_V_GEN)cp $(srcdir)/%D%/$(CONFIG).texi %D%/asconfig.texi && touch -m -r $(srcdir)/%D%/$(CONFIG).texi %D%/asconfig.texi $(AM_V_at)chmod u+w %D%/asconfig.texi CPU_DOCS = \ |