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-rw-r--r--gas/config/obj-elf.h5
-rw-r--r--gas/config/obj-som.h5
-rw-r--r--gas/config/tc-arc.c14
-rw-r--r--gas/config/tc-csky.c40
-rw-r--r--gas/config/tc-d10v.c3
-rw-r--r--gas/config/tc-hppa.h6
-rw-r--r--gas/config/tc-iq2000.h2
-rw-r--r--gas/config/tc-m32r.h8
-rw-r--r--gas/config/tc-mt.h3
-rw-r--r--gas/config/tc-nds32.h3
-rw-r--r--gas/config/tc-pdp11.c3
-rw-r--r--gas/config/tc-score.c2
-rw-r--r--gas/config/tc-score7.c4
-rw-r--r--gas/config/tc-tic6x.c12
-rw-r--r--gas/config/tc-z80.c2
15 files changed, 37 insertions, 75 deletions
diff --git a/gas/config/obj-elf.h b/gas/config/obj-elf.h
index 50eb475..c967db6 100644
--- a/gas/config/obj-elf.h
+++ b/gas/config/obj-elf.h
@@ -114,11 +114,6 @@ struct elf_section_match
#define OBJ_SYMFIELD_TYPE struct elf_obj_sy
-#ifndef FALSE
-#define FALSE 0
-#define TRUE !FALSE
-#endif
-
#ifndef obj_begin
#define obj_begin() elf_begin ()
#endif
diff --git a/gas/config/obj-som.h b/gas/config/obj-som.h
index 762ee50..a2c5315 100644
--- a/gas/config/obj-som.h
+++ b/gas/config/obj-som.h
@@ -30,11 +30,6 @@
#include "som/reloc.h"
#include "targ-cpu.h"
-#ifndef FALSE
-#define FALSE 0
-#define TRUE !FALSE
-#endif
-
/* should be conditional on address size! */
#define som_symbol(asymbol) ((som_symbol_type *) (&(asymbol)->the_bfd))
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 958eada..5b1c33e 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -1732,7 +1732,7 @@ parse_opcode_flags (const struct arc_opcode *opcode,
}
/* Did I check all the parsed flags? */
- return lnflg ? FALSE : TRUE;
+ return lnflg == 0;
}
@@ -3754,7 +3754,7 @@ relaxable_flag (const struct arc_relaxable_ins *ins,
}
/* If counttrue == nflgs, then all flags have been found. */
- return (counttrue == nflgs ? TRUE : FALSE);
+ return counttrue == nflgs;
}
/* Checks if operands are in line with relaxable insn. */
@@ -3831,7 +3831,7 @@ relaxable_operand (const struct arc_relaxable_ins *ins,
operand = &ins->operands[i];
}
- return (i == ntok ? TRUE : FALSE);
+ return i == ntok;
}
/* Return TRUE if this OPDCODE is a candidate for relaxation. */
@@ -4073,8 +4073,7 @@ assemble_insn (const struct arc_opcode *opcode,
pcrel = reloc_howto->pc_relative;
}
fixup->pcrel = pcrel;
- fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ?
- TRUE : FALSE;
+ fixup->islong = (operand->flags & ARC_OPERAND_LIMM) != 0;
break;
}
}
@@ -4675,9 +4674,8 @@ tokenize_extregister (extRegister_t *ereg, int opertype)
char c;
char *p;
int number, imode = 0;
- bfd_boolean isCore_p = (opertype == EXT_CORE_REGISTER) ? TRUE : FALSE;
- bfd_boolean isReg_p = (opertype == EXT_CORE_REGISTER
- || opertype == EXT_AUX_REGISTER) ? TRUE : FALSE;
+ bfd_boolean isCore_p = opertype == EXT_CORE_REGISTER;
+ bfd_boolean isReg_p = opertype == EXT_CORE_REGISTER || opertype == EXT_AUX_REGISTER;
/* 1st: get register name. */
SKIP_WHITESPACE ();
diff --git a/gas/config/tc-csky.c b/gas/config/tc-csky.c
index 7a74eab..583fb8b 100644
--- a/gas/config/tc-csky.c
+++ b/gas/config/tc-csky.c
@@ -3314,7 +3314,7 @@ parse_opcode (char *str)
{
/* Is csky force 32 or 16 instruction? */
if (IS_CSKY_V2 (mach_flag)
- && *opcode_end == '.' && has_suffix == FALSE)
+ && *opcode_end == '.' && !has_suffix)
{
has_suffix = TRUE;
if (IS_OPCODE32F (opcode_end))
@@ -3334,7 +3334,7 @@ parse_opcode (char *str)
}
/* Is csky force 32 or 16 instruction? */
- if (has_suffix == FALSE)
+ if (!has_suffix)
{
if (IS_CSKY_V2 (mach_flag) && IS_OPCODE32F (opcode_end))
{
@@ -3350,7 +3350,7 @@ parse_opcode (char *str)
name[nlen] = '\0';
/* Generate macro_name for finding hash in macro hash_table. */
- if (has_suffix == TRUE)
+ if (has_suffix)
nlen += 2;
strncpy (macro_name, str, nlen);
macro_name[nlen] = '\0';
@@ -3439,7 +3439,7 @@ get_operand_value (struct csky_opcode_info *op,
return FALSE;
}
- if (get_operand_value (op, oper, &soprnd->subs[0]) == FALSE)
+ if (!get_operand_value (op, oper, &soprnd->subs[0]))
{
*s = rc;
return FALSE;
@@ -3452,7 +3452,7 @@ get_operand_value (struct csky_opcode_info *op,
return FALSE;
}
- if (get_operand_value (op, oper, &soprnd->subs[1]) == FALSE)
+ if (!get_operand_value (op, oper, &soprnd->subs[1]))
{
*s = rc;
return FALSE;
@@ -3610,7 +3610,7 @@ get_operand_value (struct csky_opcode_info *op,
int val = csky_insn.val[csky_insn.idx - 1];
log = csky_log_2 (val);
csky_insn.val[csky_insn.idx - 1] = log;
- return (log == -1 ? FALSE : TRUE);
+ return log != -1;
}
else
return FALSE;
@@ -3632,7 +3632,7 @@ get_operand_value (struct csky_opcode_info *op,
}
else
csky_insn.val[csky_insn.idx - 1] = log;
- return (log == -1 ? FALSE : TRUE);
+ return log != -1;
}
else
return FALSE;
@@ -3794,11 +3794,11 @@ get_operand_value (struct csky_opcode_info *op,
else
{
csky_insn.val[csky_insn.idx] = 0;
- if (is_psr_bit (oper) != FALSE)
+ if (is_psr_bit (oper))
while (**oper == ',')
{
*oper += 1;
- if (is_psr_bit (oper) == FALSE)
+ if (!is_psr_bit (oper))
{
ret = FALSE;
break;
@@ -3806,7 +3806,7 @@ get_operand_value (struct csky_opcode_info *op,
}
else
ret = FALSE;
- if (ret == TRUE && IS_CSKY_V1 (mach_flag)
+ if (ret && IS_CSKY_V1 (mach_flag)
&& csky_insn.val[csky_insn.idx] > 8)
ret = FALSE;
}
@@ -4315,7 +4315,7 @@ parse_operands_op (char *str, struct csky_opcode_info *op)
oper++;
flag_pass = get_operand_value (&op[i], &oper,
&op[i].oprnd.oprnds[j]);
- if (flag_pass == FALSE)
+ if (!flag_pass)
break;
while (ISSPACE (*oper))
oper++;
@@ -4342,7 +4342,7 @@ parse_operands_op (char *str, struct csky_opcode_info *op)
}
/* Parse operands in one table end. */
- if (flag_pass == TRUE)
+ if (flag_pass)
{
/* Parse operands success, set opcode_idx. */
csky_insn.opcode_idx = i;
@@ -4366,7 +4366,7 @@ parse_operands (char *str)
if (csky_insn.flag_force == INSN_OPCODE16F
&& (csky_insn.opcode->isa_flag16 & isa_flag) != 0)
{
- if (parse_operands_op (oper, csky_insn.opcode->op16) == TRUE)
+ if (parse_operands_op (oper, csky_insn.opcode->op16))
{
csky_insn.isize = 2;
return TRUE;
@@ -4376,7 +4376,7 @@ parse_operands (char *str)
else if (csky_insn.flag_force == INSN_OPCODE32F
&& (csky_insn.opcode->isa_flag32 & isa_flag) != 0)
{
- if (parse_operands_op (oper, csky_insn.opcode->op32) == TRUE)
+ if (parse_operands_op (oper, csky_insn.opcode->op32))
{
csky_insn.isize = 4;
return TRUE;
@@ -4386,13 +4386,13 @@ parse_operands (char *str)
else
{
if ((csky_insn.opcode->isa_flag16 & isa_flag) != 0
- && parse_operands_op (oper, csky_insn.opcode->op16) == TRUE)
+ && parse_operands_op (oper, csky_insn.opcode->op16))
{
csky_insn.isize = 2;
return TRUE;
}
if ((csky_insn.opcode->isa_flag32 & isa_flag) != 0
- && parse_operands_op (oper, csky_insn.opcode->op32) == TRUE)
+ && parse_operands_op (oper, csky_insn.opcode->op32))
{
csky_insn.isize = 4;
return TRUE;
@@ -4559,7 +4559,7 @@ md_assemble (char *str)
while (ISSPACE (* str))
str++;
/* Get opcode from str. */
- if (parse_opcode (str) == FALSE)
+ if (!parse_opcode (str))
{
csky_show_error (ERROR_OPCODE_ILLEGAL, 0, NULL, NULL);
return;
@@ -4586,7 +4586,7 @@ md_assemble (char *str)
}
/* Parse the operands according to operand type. */
- if (parse_operands (csky_insn.opcode_end) == FALSE)
+ if (!parse_operands (csky_insn.opcode_end))
{
csky_show_error (error_state.err_num, error_state.opnum,
(void *)error_state.arg1, (void *)error_state.arg1);
@@ -4608,7 +4608,7 @@ md_assemble (char *str)
}
/* Adjust for xtrb0/xtrb1/xtrb2/xtrb3/divs/divu in csky v1 ISA. */
- if (mov_r1_after == TRUE)
+ if (mov_r1_after)
{
unsigned int mov_insn = CSKYV1_INST_MOV_RX_R1;
mov_insn |= csky_insn.val[0];
@@ -4618,7 +4618,7 @@ md_assemble (char *str)
md_number_to_chars (csky_insn.output, mov_insn, 2);
csky_insn.isize += 2;
}
- if (mov_r1_before == TRUE)
+ if (mov_r1_before)
csky_insn.isize += 2;
/* Check literal. */
diff --git a/gas/config/tc-d10v.c b/gas/config/tc-d10v.c
index d126927..547db0c 100644
--- a/gas/config/tc-d10v.c
+++ b/gas/config/tc-d10v.c
@@ -581,8 +581,7 @@ build_insn (struct d10v_opcode *opcode,
fixups->fix[fixups->fc].exp = opers[i];
fixups->fix[fixups->fc].operand = opcode->operands[i];
- fixups->fix[fixups->fc].pcrel =
- (flags & OPERAND_ADDR) ? TRUE : FALSE;
+ fixups->fix[fixups->fc].pcrel = (flags & OPERAND_ADDR) != 0;
(fixups->fc)++;
}
diff --git a/gas/config/tc-hppa.h b/gas/config/tc-hppa.h
index f620c82..b418991 100644
--- a/gas/config/tc-hppa.h
+++ b/gas/config/tc-hppa.h
@@ -80,12 +80,6 @@
#define WARN_COMMENTS 1
#endif
-/* FIXME. Why oh why aren't these defined somewhere globally? */
-#ifndef FALSE
-#define FALSE (0)
-#define TRUE (!FALSE)
-#endif
-
#define ASEC_NULL (asection *)0
/* pa_define_label gets used outside of tc-hppa.c via tc_frob_label. */
diff --git a/gas/config/tc-iq2000.h b/gas/config/tc-iq2000.h
index 940ffb4..5540f50 100644
--- a/gas/config/tc-iq2000.h
+++ b/gas/config/tc-iq2000.h
@@ -45,8 +45,6 @@
#define tc_frob_file() iq2000_frob_file ()
-#define obj_fix_adjustable(fixP) iq2000_fix_adjustable (fixP)
-
/* After creating a fixup for an instruction operand, we need to check
for HI16 relocs and queue them up for later sorting. */
#define md_cgen_record_fixup_exp iq2000_cgen_record_fixup_exp
diff --git a/gas/config/tc-m32r.h b/gas/config/tc-m32r.h
index 413b927..5ff14fb 100644
--- a/gas/config/tc-m32r.h
+++ b/gas/config/tc-m32r.h
@@ -70,7 +70,7 @@ extern void m32r_handle_align (fragS *);
#define md_apply_fix gas_cgen_md_apply_fix
#define tc_fix_adjustable(FIX) m32r_fix_adjustable (FIX)
-bfd_boolean m32r_fix_adjustable (struct fix *);
+extern bfd_boolean m32r_fix_adjustable (struct fix *);
/* After creating a fixup for an instruction operand, we need to check for
HI16 relocs and queue them up for later sorting. */
@@ -80,12 +80,6 @@ bfd_boolean m32r_fix_adjustable (struct fix *);
extern int pic_code;
-extern bfd_boolean m32r_fix_adjustable (struct fix *);
-
-/* This arranges for gas/write.c to not apply a relocation if
- obj_fix_adjustable() says it is not adjustable. */
-#define TC_FIX_ADJUSTABLE(fixP) obj_fix_adjustable (fixP)
-
#define tc_frob_file_before_fix() m32r_frob_file ()
extern void m32r_frob_file (void);
diff --git a/gas/config/tc-mt.h b/gas/config/tc-mt.h
index dd8733f..fd1cb01 100644
--- a/gas/config/tc-mt.h
+++ b/gas/config/tc-mt.h
@@ -49,9 +49,6 @@ extern void mt_apply_fix (struct fix *, valueT *, segT);
/* Call md_pcrel_from_section(), not md_pcrel_from(). */
#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
-#define obj_fix_adjustable(fixP) iq2000_fix_adjustable (fixP)
-extern bfd_boolean mt_fix_adjustable (struct fix *);
-
/* Values passed to md_apply_fix don't include the symbol value. */
#define MD_APPLY_SYM_VALUE(FIX) 0
diff --git a/gas/config/tc-nds32.h b/gas/config/tc-nds32.h
index c806de9..7dbeb59 100644
--- a/gas/config/tc-nds32.h
+++ b/gas/config/tc-nds32.h
@@ -214,9 +214,6 @@ extern int tc_nds32_regname_to_dw2regnum (char *);
&& S_IS_DEFINED ((FIX)->fx_addsy) \
&& ! S_IS_COMMON ((FIX)->fx_addsy)))
#define TC_HANDLES_FX_DONE
-/* This arranges for gas/write.c to not apply a relocation if
- obj_fix_adjustable() says it is not adjustable. */
-#define TC_FIX_ADJUSTABLE(fixP) obj_fix_adjustable (fixP)
#endif
/* Because linker may relax the code, assemble-time expression
diff --git a/gas/config/tc-pdp11.c b/gas/config/tc-pdp11.c
index 2b01fbc..b59db94 100644
--- a/gas/config/tc-pdp11.c
+++ b/gas/config/tc-pdp11.c
@@ -24,9 +24,6 @@
extern int flonum_gen2vax (int, FLONUM_TYPE * f, LITTLENUM_TYPE *);
-#define TRUE 1
-#define FALSE 0
-
/* A representation for PDP-11 machine code. */
struct pdp11_code
{
diff --git a/gas/config/tc-score.c b/gas/config/tc-score.c
index b48fd7a..9e1798d 100644
--- a/gas/config/tc-score.c
+++ b/gas/config/tc-score.c
@@ -2551,7 +2551,7 @@ s3_gen_insn_frag (struct s3_score_it *part_1, struct s3_score_it *part_2)
struct s3_score_it *inst2 = part_2;
struct s3_score_it backup_inst1;
- pce_p = (inst2) ? TRUE : FALSE;
+ pce_p = inst2 != NULL;
memcpy (&backup_inst1, inst1, sizeof (struct s3_score_it));
/* Adjust instruction opcode and to be relaxed instruction opcode. */
diff --git a/gas/config/tc-score7.c b/gas/config/tc-score7.c
index b1194b3..c3feeae 100644
--- a/gas/config/tc-score7.c
+++ b/gas/config/tc-score7.c
@@ -2672,7 +2672,7 @@ s7_gen_insn_frag (struct s7_score_it *part_1, struct s7_score_it *part_2)
struct s7_score_it *inst2 = part_2;
struct s7_score_it backup_inst1;
- pce_p = (inst2) ? TRUE : FALSE;
+ pce_p = inst2 != NULL;
memcpy (&backup_inst1, inst1, sizeof (struct s7_score_it));
/* Adjust instruction opcode and to be relaxed instruction opcode. */
@@ -6355,7 +6355,7 @@ s7_relax_frag (asection * sec ATTRIBUTE_UNUSED,
}
}
- word_align_p = ((fragp->fr_address + fragp->insn_addr) % 4 == 0) ? TRUE : FALSE;
+ word_align_p = (fragp->fr_address + fragp->insn_addr) % 4 == 0;
/* Get instruction size and relax size after the last relaxation. */
if (fragp->fr_opcode)
diff --git a/gas/config/tc-tic6x.c b/gas/config/tc-tic6x.c
index e2304c5..0160085 100644
--- a/gas/config/tc-tic6x.c
+++ b/gas/config/tc-tic6x.c
@@ -350,16 +350,14 @@ tic6x_update_features (void)
tic6x_num_registers
= (tic6x_arch_enable & (TIC6X_INSN_C64X | TIC6X_INSN_C67XP)) ? 32 : 16;
- tic6x_predicate_a0 = (tic6x_arch_enable & TIC6X_INSN_C64X) ? TRUE : FALSE;
+ tic6x_predicate_a0 = (tic6x_arch_enable & TIC6X_INSN_C64X) != 0;
tic6x_can_cross_fp_boundary
- = (tic6x_arch_enable
- & (TIC6X_INSN_C64X | TIC6X_INSN_C67XP)) ? TRUE : FALSE;
+ = (tic6x_arch_enable & (TIC6X_INSN_C64X | TIC6X_INSN_C67XP)) != 0;
- tic6x_long_data_constraints
- = (tic6x_arch_enable & TIC6X_INSN_C64X) ? FALSE : TRUE;
+ tic6x_long_data_constraints = (tic6x_arch_enable & TIC6X_INSN_C64X) == 0;
- tic6x_compact_insns = (tic6x_arch_enable & TIC6X_INSN_C64XP) ? TRUE : FALSE;
+ tic6x_compact_insns = (tic6x_arch_enable & TIC6X_INSN_C64XP) != 0;
}
/* Do configuration after all options have been parsed. */
@@ -3620,7 +3618,7 @@ md_assemble (char *str)
seginfo->tc_segment_info_data.sploop_ii,
&fix_exp, &fix_pcrel, &fx_r_type,
&fix_adda, &fix_needed, &encoded_ok,
- (try_rank == min_rank ? TRUE : FALSE),
+ try_rank == min_rank,
str, opc_len);
if (encoded_ok)
{
diff --git a/gas/config/tc-z80.c b/gas/config/tc-z80.c
index cfb433f..d4bbb56 100644
--- a/gas/config/tc-z80.c
+++ b/gas/config/tc-z80.c
@@ -1226,7 +1226,7 @@ emit_byte (expressionS * val, bfd_reloc_code_real_type r_type)
{
/* For symbols only, constants are stored at begin of function. */
fix_new_exp (frag_now, p - frag_now->fr_literal, 1, val,
- (r_type == BFD_RELOC_8_PCREL) ? TRUE : FALSE, r_type);
+ r_type == BFD_RELOC_8_PCREL, r_type);
}
}
generated by cgit v1.1 at 2024-10-10 17:39:55 +0000