diff options
Diffstat (limited to 'gas/config')
-rw-r--r-- | gas/config/bfin-parse.y | 26 | ||||
-rw-r--r-- | gas/config/tc-bfin.c | 12 | ||||
-rw-r--r-- | gas/config/tc-cris.c | 128 | ||||
-rw-r--r-- | gas/config/tc-frv.c | 2 | ||||
-rw-r--r-- | gas/config/tc-frv.h | 2 | ||||
-rw-r--r-- | gas/config/tc-hppa.c | 10 | ||||
-rw-r--r-- | gas/config/tc-hppa.h | 2 | ||||
-rw-r--r-- | gas/config/tc-i386.c | 44 | ||||
-rw-r--r-- | gas/config/tc-i386.h | 49 | ||||
-rw-r--r-- | gas/config/tc-m68k.c | 6 | ||||
-rw-r--r-- | gas/config/tc-mips.c | 10 | ||||
-rw-r--r-- | gas/config/tc-mmix.c | 15 | ||||
-rw-r--r-- | gas/config/tc-mmix.h | 3 | ||||
-rw-r--r-- | gas/config/tc-mn10300.h | 2 | ||||
-rw-r--r-- | gas/config/tc-ns32k.c | 2 | ||||
-rw-r--r-- | gas/config/tc-ppc.c | 11 | ||||
-rw-r--r-- | gas/config/tc-sh.h | 21 | ||||
-rw-r--r-- | gas/config/tc-sh64.h | 9 | ||||
-rw-r--r-- | gas/config/tc-tic4x.c | 1 | ||||
-rw-r--r-- | gas/config/tc-xtensa.c | 2 | ||||
-rw-r--r-- | gas/config/tc-xtensa.h | 2 | ||||
-rw-r--r-- | gas/config/tc-z80.c | 2 | ||||
-rw-r--r-- | gas/config/te-solaris.h | 30 |
23 files changed, 265 insertions, 126 deletions
diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y index 283b813..83cc688 100644 --- a/gas/config/bfin-parse.y +++ b/gas/config/bfin-parse.y @@ -1,5 +1,5 @@ /* bfin-parse.y ADI Blackfin parser - Copyright 2005, 2006, 2007 + Copyright 2005, 2006, 2007, 2008 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler. @@ -23,7 +23,7 @@ #include "as.h" #include <obstack.h> -#include "bfin-aux.h" // opcode generating auxiliaries +#include "bfin-aux.h" /* Opcode generating auxiliaries. */ #include "libbfd.h" #include "elf/common.h" #include "elf/bfin.h" @@ -1932,22 +1932,20 @@ asm_1: else return yyerror ("Bad shift value or register"); } - | HALF_REG ASSIGN HALF_REG LESS_LESS expr - { - if (IS_UIMM ($5, 4)) - { - notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n"); - $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3)); - } - else - return yyerror ("Bad shift value"); - } | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod { if (IS_UIMM ($5, 4)) { - notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n"); - $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3)); + if ($6.s0) + { + notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n"); + $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3)); + } + else + { + notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n"); + $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3)); + } } else return yyerror ("Bad shift value"); diff --git a/gas/config/tc-bfin.c b/gas/config/tc-bfin.c index 8dccdbc..c3b8aef 100644 --- a/gas/config/tc-bfin.c +++ b/gas/config/tc-bfin.c @@ -960,7 +960,7 @@ note_reloc2 (INSTR_T code, const char *symbol, int reloc, int value, int pcrel) INSTR_T gencode (unsigned long x) { - INSTR_T cell = (INSTR_T) obstack_alloc (&mempool, sizeof (struct bfin_insn)); + INSTR_T cell = obstack_alloc (&mempool, sizeof (struct bfin_insn)); memset (cell, 0, sizeof (struct bfin_insn)); cell->value = (x); return cell; @@ -973,7 +973,7 @@ int count_insns; static void * allocate (int n) { - return (void *) obstack_alloc (&mempool, n); + return obstack_alloc (&mempool, n); } Expr_Node * @@ -1452,14 +1452,14 @@ bfin_gen_ldstidxi (REG_T ptr, REG_T reg, int W, int sz, int Z, Expr_Node * poffs { int value, offset; switch (sz) - { // load/store access size - case 0: // 32 bit + { /* load/store access size */ + case 0: /* 32 bit */ value = EXPR_VALUE (poffset) >> 2; break; - case 1: // 16 bit + case 1: /* 16 bit */ value = EXPR_VALUE (poffset) >> 1; break; - case 2: // 8 bit + case 2: /* 8 bit */ value = EXPR_VALUE (poffset); break; default: diff --git a/gas/config/tc-cris.c b/gas/config/tc-cris.c index 325f842..c76e0d4 100644 --- a/gas/config/tc-cris.c +++ b/gas/config/tc-cris.c @@ -52,7 +52,7 @@ /* Like in ":GOT", ":GOTOFF" etc. Other ports use '@', but that's in line_separator_chars for CRIS, so we avoid it. */ -#define PIC_SUFFIX_CHAR ':' +#define RELOC_SUFFIX_CHAR ':' /* This might be CRIS_INSN_NONE if we're assembling a prefix-insn only. Note that some prefix-insns might be assembled as CRIS_INSN_NORMAL. */ @@ -150,9 +150,9 @@ static void s_cris_loc (int); static void s_cris_arch (int); /* Get ":GOT", ":GOTOFF", ":PLT" etc. suffixes. */ -static void cris_get_pic_suffix (char **, bfd_reloc_code_real_type *, - expressionS *); -static unsigned int cris_get_pic_reloc_size (bfd_reloc_code_real_type); +static void cris_get_reloc_suffix (char **, bfd_reloc_code_real_type *, + expressionS *); +static unsigned int cris_get_specified_reloc_size (bfd_reloc_code_real_type); /* All the .syntax functions. */ static void cris_force_reg_prefix (void); @@ -183,6 +183,9 @@ static bfd_boolean symbols_have_leading_underscore /* Whether or not we allow PIC, and expand to PIC-friendly constructs. */ static bfd_boolean pic = FALSE; +/* Whether or not we allow TLS suffixes. For the moment, we always do. */ +static const bfd_boolean tls = TRUE; + /* If we're configured for "cris", default to allow all v0..v10 instructions and register names. */ #ifndef DEFAULT_CRIS_ARCH @@ -1252,7 +1255,7 @@ md_assemble (char *str) /* When the expression is unknown for a BDAP, it can need 0, 2 or 4 extra bytes, so we handle it separately. */ case PREFIX_BDAP_IMM: - /* We only do it if the relocation is unspecified, i.e. not a PIC + /* We only do it if the relocation is unspecified, i.e. not a PIC or TLS relocation. */ if (prefix.reloc == BFD_RELOC_NONE) { @@ -1269,13 +1272,13 @@ md_assemble (char *str) md_number_to_chars (opcodep, (long) prefix.opcode, 2); /* Having a specified reloc only happens for DIP and for BDAP with - PIC operands, but it is ok to drop through here for the other + PIC or TLS operands, but it is ok to drop through here for the other prefixes as they can have no relocs specified. */ if (prefix.reloc != BFD_RELOC_NONE) { unsigned int relocsize = (prefix.kind == PREFIX_DIP - ? 4 : cris_get_pic_reloc_size (prefix.reloc)); + ? 4 : cris_get_specified_reloc_size (prefix.reloc)); p = frag_more (relocsize); fix_new_exp (frag_now, (p - frag_now->fr_literal), relocsize, @@ -1889,7 +1892,7 @@ cris_process_instruction (char *insn_text, struct cris_instruction *out_insnp, whether or not this is autoincrement mode. */ out_insnp->opcode |= (mode << 10); - /* If there was a PIC reloc specifier, then it was + /* If there was a reloc specifier, then it was attached to the prefix. Note that we can't check that the reloc size matches, since we don't have all the operands yet in all cases. */ @@ -1903,8 +1906,8 @@ cris_process_instruction (char *insn_text, struct cris_instruction *out_insnp, case 'N': case 'Y': - /* Like 's', but immediate operand only. Also does not - modify insn. There are no insns where a PIC reloc + /* Like 's', but immediate operand only. Also do not + modify insn. There are no insns where an explicit reloc specifier makes sense. */ if (cris_get_expression (&s, &out_insnp->expr)) { @@ -1927,9 +1930,10 @@ cris_process_instruction (char *insn_text, struct cris_instruction *out_insnp, relocation. */ out_insnp->expr.X_add_number += 6; - if (pic && *s == PIC_SUFFIX_CHAR) - cris_get_pic_suffix (&s, &out_insnp->reloc, - &out_insnp->expr); + /* TLS specifiers do not make sense here. */ + if (pic && *s == RELOC_SUFFIX_CHAR) + cris_get_reloc_suffix (&s, &out_insnp->reloc, + &out_insnp->expr); continue; } @@ -2194,13 +2198,17 @@ cris_process_instruction (char *insn_text, struct cris_instruction *out_insnp, } /* If there was a relocation specified for the immediate - expression (i.e. it had a PIC modifier) check that the - size of the PIC relocation matches the size specified by + expression (i.e. it had a PIC or TLS modifier) check that the + size of the relocation matches the size specified by the opcode. */ if (out_insnp->reloc != BFD_RELOC_NONE - && (cris_get_pic_reloc_size (out_insnp->reloc) + && (cris_get_specified_reloc_size (out_insnp->reloc) != (unsigned int) out_insnp->imm_oprnd_size)) - as_bad (_("PIC relocation size does not match operand size")); + as_bad (out_insnp->reloc == BFD_RELOC_CRIS_32_GD + || out_insnp->reloc == BFD_RELOC_CRIS_32_TPREL + || out_insnp->reloc == BFD_RELOC_CRIS_16_TPREL + ? _("TLS relocation size does not match operand size") + : _("PIC relocation size does not match operand size")); } else if (instruction->op == cris_muls_op || instruction->op == cris_mulu_op) @@ -2715,8 +2723,8 @@ get_autoinc_prefix_or_indir_op (char **cPP, struct cris_prefix *prefixp, /* We tentatively put an opcode corresponding to a 32-bit operand here, although it may be - relaxed when there's no PIC specifier for the - operand. */ + relaxed when there's no relocation + specifier for the operand. */ prefixp->opcode = (BDAP_INDIR_OPCODE | (prefixp->base_reg_number << 12) @@ -2726,18 +2734,18 @@ get_autoinc_prefix_or_indir_op (char **cPP, struct cris_prefix *prefixp, /* This can have a PIC suffix, specifying reloc type to use. */ - if (pic && **cPP == PIC_SUFFIX_CHAR) + if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR) { unsigned int relocsize; - cris_get_pic_suffix (cPP, &prefixp->reloc, - &prefixp->expr); + cris_get_reloc_suffix (cPP, &prefixp->reloc, + &prefixp->expr); /* Tweak the size of the immediate operand in the prefix opcode if it isn't what we set. */ relocsize - = cris_get_pic_reloc_size (prefixp->reloc); + = cris_get_specified_reloc_size (prefixp->reloc); if (relocsize != 4) prefixp->opcode = ((prefixp->opcode & ~(3 << 4)) @@ -2763,8 +2771,9 @@ get_autoinc_prefix_or_indir_op (char **cPP, struct cris_prefix *prefixp, in the blanks and break out to match the final ']'. - Note that we don't allow a PIC suffix for an - operand with a minus sign. */ + Note that we don't allow a relocation + suffix for an operand with a minus + sign. */ prefixp->kind = PREFIX_BDAP_IMM; break; } @@ -2802,8 +2811,8 @@ get_autoinc_prefix_or_indir_op (char **cPP, struct cris_prefix *prefixp, /* This can have a PIC suffix, specifying reloc type to use. The caller must check that the reloc size matches the operand size. */ - if (pic && **cPP == PIC_SUFFIX_CHAR) - cris_get_pic_suffix (cPP, &prefixp->reloc, imm_exprP); + if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR) + cris_get_reloc_suffix (cPP, &prefixp->reloc, imm_exprP); return 1; } @@ -2971,15 +2980,15 @@ get_3op_or_dip_prefix_op (char **cPP, struct cris_prefix *prefixp) | REG_PC /* << 0 */); /* This can have a PIC suffix, specifying reloc type to use. */ - if (pic && **cPP == PIC_SUFFIX_CHAR) + if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR) { unsigned int relocsize; - cris_get_pic_suffix (cPP, &prefixp->reloc, &prefixp->expr); + cris_get_reloc_suffix (cPP, &prefixp->reloc, &prefixp->expr); /* Tweak the size of the immediate operand in the prefix opcode if it isn't what we set. */ - relocsize = cris_get_pic_reloc_size (prefixp->reloc); + relocsize = cris_get_specified_reloc_size (prefixp->reloc); if (relocsize != 4) prefixp->opcode = ((prefixp->opcode & ~(3 << 4)) @@ -3426,13 +3435,19 @@ gen_cond_branch_32 (char *opcodep, char *writep, fragS *fragP, md_number_to_chars (writep + 8, MOVE_PC_INCR_OPCODE_SUFFIX, 2); } -/* Get the size of an immediate-reloc in bytes. Only valid for PIC - relocs. */ +/* Get the size of an immediate-reloc in bytes. Only valid for + specified relocs (TLS, PIC). */ static unsigned int -cris_get_pic_reloc_size (bfd_reloc_code_real_type reloc) +cris_get_specified_reloc_size (bfd_reloc_code_real_type reloc) { - return reloc == BFD_RELOC_CRIS_16_GOTPLT || reloc == BFD_RELOC_CRIS_16_GOT + return + reloc == BFD_RELOC_CRIS_16_GOTPLT + || reloc == BFD_RELOC_CRIS_16_GOT + || reloc == BFD_RELOC_CRIS_16_GOT_GD + || reloc == BFD_RELOC_CRIS_16_DTPREL + || reloc == BFD_RELOC_CRIS_16_GOT_TPREL + || reloc == BFD_RELOC_CRIS_16_TPREL ? 2 : 4; } @@ -3440,8 +3455,8 @@ cris_get_pic_reloc_size (bfd_reloc_code_real_type reloc) Adjust *EXPRP with any addend found after the PIC suffix. */ static void -cris_get_pic_suffix (char **cPP, bfd_reloc_code_real_type *relocp, - expressionS *exprP) +cris_get_reloc_suffix (char **cPP, bfd_reloc_code_real_type *relocp, + expressionS *exprP) { char *s = *cPP; unsigned int i; @@ -3452,10 +3467,14 @@ cris_get_pic_suffix (char **cPP, bfd_reloc_code_real_type *relocp, const char *const suffix; unsigned int len; bfd_reloc_code_real_type reloc; + bfd_boolean pic_p; + bfd_boolean tls_p; } pic_suffixes[] = { #undef PICMAP -#define PICMAP(s, r) {s, sizeof (s) - 1, r} +#define PICMAP(s, r) {s, sizeof (s) - 1, r, TRUE, FALSE} +#define PICTLSMAP(s, r) {s, sizeof (s) - 1, r, TRUE, TRUE} +#define TLSMAP(s, r) {s, sizeof (s) - 1, r, FALSE, TRUE} /* Keep this in order with longest unambiguous prefix first. */ PICMAP ("GOTPLT16", BFD_RELOC_CRIS_16_GOTPLT), PICMAP ("GOTPLT", BFD_RELOC_CRIS_32_GOTPLT), @@ -3463,7 +3482,16 @@ cris_get_pic_suffix (char **cPP, bfd_reloc_code_real_type *relocp, PICMAP ("PLT", BFD_RELOC_CRIS_32_PLT_PCREL), PICMAP ("GOTOFF", BFD_RELOC_CRIS_32_GOTREL), PICMAP ("GOT16", BFD_RELOC_CRIS_16_GOT), - PICMAP ("GOT", BFD_RELOC_CRIS_32_GOT) + PICMAP ("GOT", BFD_RELOC_CRIS_32_GOT), + PICTLSMAP ("GDGOTREL16", BFD_RELOC_CRIS_16_GOT_GD), + PICTLSMAP ("GDGOTREL", BFD_RELOC_CRIS_32_GOT_GD), + TLSMAP ("GD", BFD_RELOC_CRIS_32_GD), + PICTLSMAP ("DTPREL16", BFD_RELOC_CRIS_16_DTPREL), + PICTLSMAP ("DTPREL", BFD_RELOC_CRIS_32_DTPREL), + PICTLSMAP ("TPOFFGOT16", BFD_RELOC_CRIS_16_GOT_TPREL), + PICTLSMAP ("TPOFFGOT", BFD_RELOC_CRIS_32_GOT_TPREL), + TLSMAP ("TPOFF16", BFD_RELOC_CRIS_16_TPREL), + TLSMAP ("TPOFF", BFD_RELOC_CRIS_32_TPREL) }; /* We've already seen the ':', so consume it. */ @@ -3472,7 +3500,11 @@ cris_get_pic_suffix (char **cPP, bfd_reloc_code_real_type *relocp, for (i = 0; i < sizeof (pic_suffixes)/sizeof (pic_suffixes[0]); i++) { if (strncmp (s, pic_suffixes[i].suffix, pic_suffixes[i].len) == 0 - && ! is_part_of_name (s[pic_suffixes[i].len])) + && ! is_part_of_name (s[pic_suffixes[i].len]) + /* PIC and non-PIC relocations are exclusive. */ + && (pic != 0) == (pic_suffixes[i].pic_p != 0) + /* But TLS can be active for non-TLS relocations too. */ + && (pic_suffixes[i].tls_p == 0 || tls)) { /* We have a match. Consume the suffix and set the relocation type. */ @@ -3599,6 +3631,15 @@ cris_number_to_imm (char *bufp, long val, int n, fixS *fixP, segT seg) case BFD_RELOC_CRIS_32_GOTPLT: case BFD_RELOC_CRIS_32_PLT_GOTREL: case BFD_RELOC_CRIS_32_PLT_PCREL: + case BFD_RELOC_CRIS_32_GOT_GD: + case BFD_RELOC_CRIS_16_GOT_GD: + case BFD_RELOC_CRIS_32_GD: + case BFD_RELOC_CRIS_32_DTPREL: + case BFD_RELOC_CRIS_16_DTPREL: + case BFD_RELOC_CRIS_32_GOT_TPREL: + case BFD_RELOC_CRIS_16_GOT_TPREL: + case BFD_RELOC_CRIS_32_TPREL: + case BFD_RELOC_CRIS_16_TPREL: /* We don't want to put in any kind of non-zero bits in the data being relocated for these. */ break; @@ -3870,6 +3911,15 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP) case BFD_RELOC_CRIS_UNSIGNED_8: case BFD_RELOC_CRIS_UNSIGNED_16: case BFD_RELOC_CRIS_LAPCQ_OFFSET: + case BFD_RELOC_CRIS_32_GOT_GD: + case BFD_RELOC_CRIS_16_GOT_GD: + case BFD_RELOC_CRIS_32_GD: + case BFD_RELOC_CRIS_32_DTPREL: + case BFD_RELOC_CRIS_16_DTPREL: + case BFD_RELOC_CRIS_32_GOT_TPREL: + case BFD_RELOC_CRIS_16_GOT_TPREL: + case BFD_RELOC_CRIS_32_TPREL: + case BFD_RELOC_CRIS_16_TPREL: code = fixP->fx_r_type; break; default: diff --git a/gas/config/tc-frv.c b/gas/config/tc-frv.c index e58def9..4551d75 100644 --- a/gas/config/tc-frv.c +++ b/gas/config/tc-frv.c @@ -1475,7 +1475,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg) case BFD_RELOC_FRV_TLSDESC_RELAX: case BFD_RELOC_FRV_GETTLSOFF_RELAX: case BFD_RELOC_FRV_TLSOFF_RELAX: - fixP->fx_addsy = expr_build_uconstant (0); + fixP->fx_addsy = abs_section_sym; break; } else diff --git a/gas/config/tc-frv.h b/gas/config/tc-frv.h index ad7eee0..732dacd 100644 --- a/gas/config/tc-frv.h +++ b/gas/config/tc-frv.h @@ -61,7 +61,7 @@ extern int frv_force_relocation (struct fix *); /* If we simplify subtractions that aren't SUB_SAME or SUB_ABS, we end up with PCrel fixups, but since we don't have any PCrel relocs, we crash. Preventing simplification gets us a good, early error. */ -#define TC_FORCE_RELOCATION_SUB_LOCAL(fixP) 1 +#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) 1 #undef GAS_CGEN_MAX_FIXUPS #define GAS_CGEN_MAX_FIXUPS 1 diff --git a/gas/config/tc-hppa.c b/gas/config/tc-hppa.c index da84526..7bb7966 100644 --- a/gas/config/tc-hppa.c +++ b/gas/config/tc-hppa.c @@ -8676,9 +8676,19 @@ hppa_regname_to_dw2regnum (char *regname) { p = regname + 2; regnum = strtoul (p, &q, 10); +#if TARGET_ARCH_SIZE == 64 if (p == q || *q || regnum <= 4 || regnum >= 32) return -1; regnum += 32 - 4; +#else + if (p == q + || (*q && ((*q != 'L' && *q != 'R') || *(q + 1))) + || regnum <= 4 || regnum >= 32) + return -1; + regnum = (regnum - 4) * 2 + 32; + if (*q == 'R') + regnum++; +#endif } return regnum; } diff --git a/gas/config/tc-hppa.h b/gas/config/tc-hppa.h index 498cb25..05168b1 100644 --- a/gas/config/tc-hppa.h +++ b/gas/config/tc-hppa.h @@ -155,7 +155,7 @@ int hppa_fix_adjustable (struct fix *); difference expression can't be used between text and data symbols, or between symbols in different executable modules. */ #define DIFF_EXPR_OK 1 -#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX) 1 +#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) 1 #define UNDEFINED_DIFFERENCE_OK #endif diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 539ea79..71abb01 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -150,25 +150,6 @@ typedef struct } sib_byte; -enum processor_type -{ - PROCESSOR_UNKNOWN, - PROCESSOR_I386, - PROCESSOR_I486, - PROCESSOR_PENTIUM, - PROCESSOR_PENTIUMPRO, - PROCESSOR_PENTIUM4, - PROCESSOR_NOCONA, - PROCESSOR_CORE, - PROCESSOR_CORE2, - PROCESSOR_K6, - PROCESSOR_ATHLON, - PROCESSOR_K8, - PROCESSOR_GENERIC32, - PROCESSOR_GENERIC64, - PROCESSOR_AMDFAM10 -}; - /* x86 arch names, types and features */ typedef struct { @@ -468,16 +449,16 @@ static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; static int cpu_arch_tune_set = 0; /* Cpu we are generating instructions for. */ -static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; +enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; /* CPU feature flags of cpu we are generating instructions for. */ static i386_cpu_flags cpu_arch_tune_flags; /* CPU instruction set architecture used. */ -static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; +enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; /* CPU feature flags of instruction set architecture used. */ -static i386_cpu_flags cpu_arch_isa_flags; +i386_cpu_flags cpu_arch_isa_flags; /* If set, conditional jumps are not automatically promoted to handle larger than a byte offset. */ @@ -993,7 +974,7 @@ i386_align_code (fragS *fragP, int count) { const char *const *patt = NULL; - if (cpu_arch_isa == PROCESSOR_UNKNOWN) + if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) { /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ switch (cpu_arch_tune) @@ -1001,7 +982,7 @@ i386_align_code (fragS *fragP, int count) case PROCESSOR_UNKNOWN: /* We use cpu_arch_isa_flags to check if we SHOULD optimize for Cpu686. */ - if (cpu_arch_isa_flags.bitfield.cpui686) + if (fragP->tc_frag_data.isa_flags.bitfield.cpui686) patt = alt_long_patt; else patt = f32_patt; @@ -1030,7 +1011,7 @@ i386_align_code (fragS *fragP, int count) } else { - switch (cpu_arch_tune) + switch (fragP->tc_frag_data.tune) { case PROCESSOR_UNKNOWN: /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be @@ -1048,7 +1029,7 @@ i386_align_code (fragS *fragP, int count) case PROCESSOR_GENERIC32: /* We use cpu_arch_isa_flags to check if we CAN optimize for Cpu686. */ - if (cpu_arch_isa_flags.bitfield.cpui686) + if (fragP->tc_frag_data.isa_flags.bitfield.cpui686) patt = alt_short_patt; else patt = f32_patt; @@ -1058,7 +1039,7 @@ i386_align_code (fragS *fragP, int count) case PROCESSOR_NOCONA: case PROCESSOR_CORE: case PROCESSOR_CORE2: - if (cpu_arch_isa_flags.bitfield.cpui686) + if (fragP->tc_frag_data.isa_flags.bitfield.cpui686) patt = alt_long_patt; else patt = f32_patt; @@ -10105,6 +10086,15 @@ i386_elf_section_type (const char *str, size_t len) return -1; } +#ifdef TE_SOLARIS +void +i386_solaris_fix_up_eh_frame (segT sec) +{ + if (flag_code == CODE_64BIT) + elf_section_type (sec) = SHT_X86_64_UNWIND; +} +#endif + #ifdef TE_PE void tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) diff --git a/gas/config/tc-i386.h b/gas/config/tc-i386.h index a670ff9..f7f829c 100644 --- a/gas/config/tc-i386.h +++ b/gas/config/tc-i386.h @@ -187,6 +187,50 @@ void i386_print_statistics (FILE *); #define md_number_to_chars number_to_chars_littleendian +enum processor_type +{ + PROCESSOR_UNKNOWN, + PROCESSOR_I386, + PROCESSOR_I486, + PROCESSOR_PENTIUM, + PROCESSOR_PENTIUMPRO, + PROCESSOR_PENTIUM4, + PROCESSOR_NOCONA, + PROCESSOR_CORE, + PROCESSOR_CORE2, + PROCESSOR_K6, + PROCESSOR_ATHLON, + PROCESSOR_K8, + PROCESSOR_GENERIC32, + PROCESSOR_GENERIC64, + PROCESSOR_AMDFAM10 +}; + +extern enum processor_type cpu_arch_tune; +extern enum processor_type cpu_arch_isa; +extern i386_cpu_flags cpu_arch_isa_flags; + +struct i386_tc_frag_data +{ + enum processor_type isa; + i386_cpu_flags isa_flags; + enum processor_type tune; +}; + +/* We need to emit the right NOP pattern in .align frags. This is + done after the text-to-bits assembly pass, so we need to mark it with + the isa/tune settings at the time the .align was assembled. */ +#define TC_FRAG_TYPE struct i386_tc_frag_data + +#define TC_FRAG_INIT(FRAGP) \ + do \ + { \ + (FRAGP)->tc_frag_data.isa = cpu_arch_isa; \ + (FRAGP)->tc_frag_data.isa_flags = cpu_arch_isa_flags; \ + (FRAGP)->tc_frag_data.tune = cpu_arch_tune; \ + } \ + while (0) + #ifdef SCO_ELF #define tc_init_after_args() sco_id () extern void sco_id (void); @@ -212,6 +256,11 @@ extern void tc_x86_frame_initial_instructions (void); #define md_elf_section_type(str,len) i386_elf_section_type (str, len) extern int i386_elf_section_type (const char *, size_t); +#ifdef TE_SOLARIS +#define md_fix_up_eh_frame(sec) i386_solaris_fix_up_eh_frame (sec) +extern void i386_solaris_fix_up_eh_frame (segT); +#endif + /* Support for SHF_X86_64_LARGE */ extern int x86_64_section_word (char *, size_t); extern int x86_64_section_letter (int, char **); diff --git a/gas/config/tc-m68k.c b/gas/config/tc-m68k.c index f3e3cf5..4f2e2f8 100644 --- a/gas/config/tc-m68k.c +++ b/gas/config/tc-m68k.c @@ -4422,7 +4422,7 @@ md_begin (void) obstack_begin (&robyn, 4000); for (i = 0; i < m68k_numopcodes; i++) { - hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant)); + hack = slak = obstack_alloc (&robyn, sizeof (struct m68k_incant)); do { ins = m68k_sorted_opcodes[i]; @@ -6184,8 +6184,8 @@ swap_mri_condition (int cc) case MCC ('g', 't'): return MCC ('l', 't'); case MCC ('l', 'e'): return MCC ('g', 'e'); /* Issue a warning for conditions we can not swap. */ - case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here - case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem + case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */ + case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */ case MCC ('v', 'c'): case MCC ('v', 's'): default : diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index f55961b..5c65384 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -1949,17 +1949,17 @@ md_begin (void) helps us detect invalid uses of them. */ for (i = 0; reg_names[i].name; i++) symbol_table_insert (symbol_new (reg_names[i].name, reg_section, - reg_names[i].num, // & RNUM_MASK, + reg_names[i].num, /* & RNUM_MASK, */ &zero_address_frag)); if (HAVE_NEWABI) for (i = 0; reg_names_n32n64[i].name; i++) symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, - reg_names_n32n64[i].num, // & RNUM_MASK, + reg_names_n32n64[i].num, /* & RNUM_MASK, */ &zero_address_frag)); else for (i = 0; reg_names_o32[i].name; i++) symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, - reg_names_o32[i].num, // & RNUM_MASK, + reg_names_o32[i].num, /* & RNUM_MASK, */ &zero_address_frag)); mips_no_prev_insn (); @@ -15163,8 +15163,6 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, - /* MIPS 64 Release 2 */ - /* Broadcom SB-1 CPU core */ { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, ISA_MIPS64, CPU_SB1 }, @@ -15172,6 +15170,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, ISA_MIPS64, CPU_SB1 }, + /* MIPS 64 Release 2 */ + /* Cavium Networks Octeon CPU core */ { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, diff --git a/gas/config/tc-mmix.c b/gas/config/tc-mmix.c index c2b3789..320ed2b 100644 --- a/gas/config/tc-mmix.c +++ b/gas/config/tc-mmix.c @@ -1365,6 +1365,9 @@ md_assemble (char *str) pass expressions as symbols and use fix_new, not fix_new_exp. */ sym = make_expr_symbol (exp + 1); + /* Mark the symbol as being OK for a reloc. */ + symbol_get_bfdsym (sym)->flags |= BSF_KEEP; + /* Now we know it can be a "base address plus offset". Add proper fixup types so we can handle this later, when we've parsed everything. */ @@ -3448,6 +3451,7 @@ mmix_md_end (void) { fragS *fragP; symbolS *mainsym; + asection *regsec; int i; /* The first frag of GREG:s going into the register contents section. */ @@ -3512,9 +3516,9 @@ mmix_md_end (void) and the same allocation order (within a file) as mmixal. */ segT this_segment = now_seg; subsegT this_subsegment = now_subseg; - asection *regsec - = bfd_make_section_old_way (stdoutput, - MMIX_REG_CONTENTS_SECTION_NAME); + + regsec = bfd_make_section_old_way (stdoutput, + MMIX_REG_CONTENTS_SECTION_NAME); subseg_set (regsec, 0); /* Finally emit the initialization-value. Emit a variable frag, which @@ -3541,6 +3545,11 @@ mmix_md_end (void) subseg_set (this_segment, this_subsegment); } + regsec = bfd_get_section_by_name (stdoutput, MMIX_REG_CONTENTS_SECTION_NAME); + /* Mark the section symbol as being OK for a reloc. */ + if (regsec != NULL) + regsec->symbol->flags |= BSF_KEEP; + /* Iterate over frags resulting from GREGs and move those that evidently have the same value together and point one to another. diff --git a/gas/config/tc-mmix.h b/gas/config/tc-mmix.h index 0e72d98..1fa3463 100644 --- a/gas/config/tc-mmix.h +++ b/gas/config/tc-mmix.h @@ -224,3 +224,6 @@ extern void mmix_md_do_align (int, char *, int, int); /* This target is buggy, and sets fix size too large. */ #define TC_FX_SIZE_SLACK(FIX) 6 + +/* MMIX has global register symbols. */ +#define TC_GLOBAL_REGISTER_SYMBOL_OK diff --git a/gas/config/tc-mn10300.h b/gas/config/tc-mn10300.h index 63ca74a..2fffaa3 100644 --- a/gas/config/tc-mn10300.h +++ b/gas/config/tc-mn10300.h @@ -70,7 +70,7 @@ void mn10300_cons_fix_new (fragS *, int, int, expressionS *); /* We validate subtract arguments within tc_gen_reloc(), so don't report errors at this point. */ -#define TC_VALIDATE_FIX_SUB(FIX) 1 +#define TC_VALIDATE_FIX_SUB(FIX, SEG) 1 /* Fixup debug sections since we will never relax them. Ideally, we could do away with this and instead check every single fixup with diff --git a/gas/config/tc-ns32k.c b/gas/config/tc-ns32k.c index 66aeae8..509239b 100644 --- a/gas/config/tc-ns32k.c +++ b/gas/config/tc-ns32k.c @@ -880,7 +880,7 @@ bit_fix_new (int size, /* Length of bitfield. */ { bit_fixS *bit_fixP; - bit_fixP = (bit_fixS *) obstack_alloc (¬es, sizeof (bit_fixS)); + bit_fixP = obstack_alloc (¬es, sizeof (bit_fixS)); bit_fixP->fx_bit_size = size; bit_fixP->fx_bit_offset = offset; diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c index 76a9e8e..648ed72 100644 --- a/gas/config/tc-ppc.c +++ b/gas/config/tc-ppc.c @@ -1428,15 +1428,8 @@ ppc_setup_opcodes (void) && ((op->flags & PPC_OPCODE_BOOKE64) == 0 || (ppc_cpu & PPC_OPCODE_BOOKE64) == PPC_OPCODE_BOOKE64 || (ppc_cpu & PPC_OPCODE_BOOKE) == 0) - && ((op->flags & (PPC_OPCODE_POWER4 | PPC_OPCODE_NOPOWER4)) == 0 - || ((op->flags & PPC_OPCODE_POWER4) - == (ppc_cpu & PPC_OPCODE_POWER4))) - && ((op->flags & PPC_OPCODE_POWER5) == 0 - || ((op->flags & PPC_OPCODE_POWER5) - == (ppc_cpu & PPC_OPCODE_POWER5))) - && ((op->flags & PPC_OPCODE_POWER6) == 0 - || ((op->flags & PPC_OPCODE_POWER6) - == (ppc_cpu & PPC_OPCODE_POWER6)))) + && ((ppc_cpu & PPC_OPCODE_POWER4) == 0 + || (op->flags & PPC_OPCODE_NOPOWER4) == 0)) { const char *retval; diff --git a/gas/config/tc-sh.h b/gas/config/tc-sh.h index dfdabd4..51b6561 100644 --- a/gas/config/tc-sh.h +++ b/gas/config/tc-sh.h @@ -83,8 +83,9 @@ extern int sh_force_relocation (struct fix *); || (sh_relax && SWITCH_TABLE (FIX))) /* Don't complain when we leave fx_subsy around. */ -#define TC_VALIDATE_FIX_SUB(FIX) \ - (sh_relax && SWITCH_TABLE (FIX)) +#define TC_VALIDATE_FIX_SUB(FIX, SEG) \ + ((md_register_arithmetic || (SEG) != reg_section) \ + && sh_relax && SWITCH_TABLE (FIX)) #define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC) extern long md_pcrel_from_section (struct fix *, segT); @@ -207,18 +208,22 @@ extern bfd_boolean sh_fix_adjustable (struct fix *); || (FIX)->fx_r_type == BFD_RELOC_SH_GOTPC \ || TC_FORCE_RELOCATION (FIX)) -#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX) (sh_relax && SWITCH_TABLE (FIX)) +#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) \ + ((!md_register_arithmetic && (SEG) == reg_section) \ + || (sh_relax && SWITCH_TABLE (FIX))) /* This keeps the subtracted symbol around, for use by PLT_PCREL relocs. */ -#define TC_FORCE_RELOCATION_SUB_ABS(FIX) \ - ((FIX)->fx_r_type == BFD_RELOC_32_PLT_PCREL) +#define TC_FORCE_RELOCATION_SUB_ABS(FIX, SEG) \ + ((FIX)->fx_r_type == BFD_RELOC_32_PLT_PCREL \ + || (!md_register_arithmetic && (SEG) == reg_section)) /* Don't complain when we leave fx_subsy around. */ #undef TC_VALIDATE_FIX_SUB -#define TC_VALIDATE_FIX_SUB(FIX) \ - ((FIX)->fx_r_type == BFD_RELOC_32_PLT_PCREL \ - || (sh_relax && SWITCH_TABLE (FIX))) +#define TC_VALIDATE_FIX_SUB(FIX, SEG) \ + ((md_register_arithmetic || (SEG) != reg_section) \ + && ((FIX)->fx_r_type == BFD_RELOC_32_PLT_PCREL \ + || (sh_relax && SWITCH_TABLE (FIX)))) #define md_parse_name(name, exprP, mode, nextcharP) \ sh_parse_name ((name), (exprP), (mode), (nextcharP)) diff --git a/gas/config/tc-sh64.h b/gas/config/tc-sh64.h index 23e72f6..17f0900 100644 --- a/gas/config/tc-sh64.h +++ b/gas/config/tc-sh64.h @@ -115,10 +115,11 @@ extern int sh64_target_mach (void); /* Don't complain when we leave fx_subsy around. */ #undef TC_VALIDATE_FIX_SUB -#define TC_VALIDATE_FIX_SUB(FIX) \ - ((FIX)->fx_r_type == BFD_RELOC_32_PLT_PCREL \ - || (sh_relax && SWITCH_TABLE (FIX)) \ - || *symbol_get_tc ((FIX)->fx_addsy) != NULL) +#define TC_VALIDATE_FIX_SUB(FIX, SEG) \ + ((md_register_arithmetic || (SEG) != reg_section) \ + && ((FIX)->fx_r_type == BFD_RELOC_32_PLT_PCREL \ + || (sh_relax && SWITCH_TABLE (FIX)) \ + || *symbol_get_tc ((FIX)->fx_addsy) != NULL)) /* Note the kludge: we want to put back C, and we also want to consume the expression, since we have handled it ourselves. FIXME: What we really diff --git a/gas/config/tc-tic4x.c b/gas/config/tc-tic4x.c index c373e20..bc92de2 100644 --- a/gas/config/tc-tic4x.c +++ b/gas/config/tc-tic4x.c @@ -821,6 +821,7 @@ tic4x_globl (int ignore ATTRIBUTE_UNUSED) *input_line_pointer = c; SKIP_WHITESPACE (); S_SET_STORAGE_CLASS (symbolP, C_EXT); + S_SET_EXTERNAL (symbolP); if (c == ',') { input_line_pointer++; diff --git a/gas/config/tc-xtensa.c b/gas/config/tc-xtensa.c index b893cef..b6c35ec 100644 --- a/gas/config/tc-xtensa.c +++ b/gas/config/tc-xtensa.c @@ -11058,7 +11058,7 @@ init_op_placement_info_table (void) { op_placement_info *opi = &op_placement_table[opcode]; /* FIXME: Make tinsn allocation dynamic. */ - if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS) + if (xtensa_opcode_num_operands (isa, opcode) > MAX_INSN_ARGS) as_fatal (_("too many operands in instruction")); opi->narrowest = XTENSA_UNDEFINED; opi->narrowest_size = 0x7F; diff --git a/gas/config/tc-xtensa.h b/gas/config/tc-xtensa.h index 987b82a..dbb5267 100644 --- a/gas/config/tc-xtensa.h +++ b/gas/config/tc-xtensa.h @@ -335,7 +335,7 @@ extern char *xtensa_section_rename (char *); #define TC_FORCE_RELOCATION(fix) xtensa_force_relocation (fix) #define TC_FORCE_RELOCATION_SUB_SAME(fix, seg) \ (! SEG_NORMAL (seg) || xtensa_force_relocation (fix)) -#define TC_VALIDATE_FIX_SUB(fix) xtensa_validate_fix_sub (fix) +#define TC_VALIDATE_FIX_SUB(fix, seg) xtensa_validate_fix_sub (fix) #define NO_PSEUDO_DOT xtensa_check_inside_bundle () #define tc_canonicalize_symbol_name(s) xtensa_section_rename (s) #define tc_canonicalize_section_name(s) xtensa_section_rename (s) diff --git a/gas/config/tc-z80.c b/gas/config/tc-z80.c index 89a4603..825d920 100644 --- a/gas/config/tc-z80.c +++ b/gas/config/tc-z80.c @@ -1471,7 +1471,7 @@ emit_ldreg (int dest, expressionS * src) && (src->X_add_number == REG_BC || src->X_add_number == REG_DE)) { q = frag_more (1); - *q = 0x0A + ((dest & 1) << 4); + *q = 0x0A + ((src->X_add_number & 1) << 4); break; } diff --git a/gas/config/te-solaris.h b/gas/config/te-solaris.h new file mode 100644 index 0000000..a3c2cea --- /dev/null +++ b/gas/config/te-solaris.h @@ -0,0 +1,30 @@ +/* Copyright 2008 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GAS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#define TE_SOLARIS + +#define LOCAL_LABELS_DOLLAR 1 +#define LOCAL_LABELS_FB 1 + +/* The Sun linker doesn't merge read-only and read-write sections into + a single read-write section so we must force all EH frame sections + to be read-write. */ +#define DWARF2_EH_FRAME_READ_ONLY 0 + +#include "obj-format.h" |