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-rw-r--r--gas/ChangeLog7
-rw-r--r--gas/config/tc-aarch64.c3
-rw-r--r--gas/doc/c-aarch64.texi3
-rw-r--r--gas/testsuite/gas/aarch64/advsimd-compnum.d40
-rw-r--r--gas/testsuite/gas/aarch64/advsimd-compnum.s9
-rw-r--r--include/ChangeLog5
-rw-r--r--include/opcode/aarch64.h4
-rw-r--r--opcodes/ChangeLog9
-rw-r--r--opcodes/aarch64-tbl.h14
9 files changed, 87 insertions, 7 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index c40140f..9213740 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
+
+ * doc/c-aarch64.texi: Add a "compnum" entry.
+ * config/tc-aarch64.c (aarch64_features): Likewise,
+ * testsuite/gas/aarch64/advsimd-compnum.s: New test.
+ * testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
+
2017-02-24 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/opcode.s: Add alternative TEST forms.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index f8cda59..46b1e70 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8438,6 +8438,9 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0),
AARCH64_FEATURE (AARCH64_FEATURE_FP
| AARCH64_FEATURE_SIMD, 0)},
+ {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0),
+ AARCH64_FEATURE (AARCH64_FEATURE_F16
+ | AARCH64_FEATURE_SIMD, 0)},
{"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0),
AARCH64_ARCH_NONE},
{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 59467c5..71d8072 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -131,6 +131,9 @@ automatically cause those extensions to be disabled.
@multitable @columnfractions .12 .17 .17 .54
@headitem Extension @tab Minimum Architecture @tab Enabled by default
@tab Description
+@item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
+ @tab Enable the complex number SIMD extensions. This implies
+ @code{fp16} and @code{simd}.
@item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
@tab Enable CRC instructions.
@item @code{crypto} @tab ARMv8-A @tab No
diff --git a/gas/testsuite/gas/aarch64/advsimd-compnum.d b/gas/testsuite/gas/aarch64/advsimd-compnum.d
new file mode 100644
index 0000000..64543a1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-compnum.d
@@ -0,0 +1,40 @@
+#as: -march=armv8.2-a+compnum -I$srcdir/$subdir
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[^:]+: 6ec3c441 fcmla v1\.2d, v2\.2d, v3\.2d, #0
+[^:]+: 6ec3cc41 fcmla v1\.2d, v2\.2d, v3\.2d, #90
+[^:]+: 6ec3d441 fcmla v1\.2d, v2\.2d, v3\.2d, #180
+[^:]+: 6ec3dc41 fcmla v1\.2d, v2\.2d, v3\.2d, #270
+[^:]+: 2e83cc41 fcmla v1\.2s, v2\.2s, v3\.2s, #90
+[^:]+: 6e83cc41 fcmla v1\.4s, v2\.4s, v3\.4s, #90
+[^:]+: 2e43cc41 fcmla v1\.4h, v2\.4h, v3\.4h, #90
+[^:]+: 6e43cc41 fcmla v1\.8h, v2\.8h, v3\.8h, #90
+[^:]+: 6f831041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #0
+[^:]+: 6f833041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #90
+[^:]+: 6f835041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #180
+[^:]+: 6f837041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #270
+[^:]+: 6f833841 fcmla v1\.4s, v2\.4s, v3\.s\[1\], #90
+[^:]+: 2f433041 fcmla v1\.4h, v2\.4h, v3\.h\[0\], #90
+[^:]+: 2f633041 fcmla v1\.4h, v2\.4h, v3\.h\[1\], #90
+[^:]+: 6f433041 fcmla v1\.8h, v2\.8h, v3\.h\[0\], #90
+[^:]+: 6f633041 fcmla v1\.8h, v2\.8h, v3\.h\[1\], #90
+[^:]+: 6f433841 fcmla v1\.8h, v2\.8h, v3\.h\[2\], #90
+[^:]+: 6f633841 fcmla v1\.8h, v2\.8h, v3\.h\[3\], #90
+[^:]+: 6ec3e441 fcadd v1\.2d, v2\.2d, v3\.2d, #90
+[^:]+: 6ec3f441 fcadd v1\.2d, v2\.2d, v3\.2d, #270
+[^:]+: 2e83e441 fcadd v1\.2s, v2\.2s, v3\.2s, #90
+[^:]+: 6e83e441 fcadd v1\.4s, v2\.4s, v3\.4s, #90
+[^:]+: 2e43e441 fcadd v1\.4h, v2\.4h, v3\.4h, #90
+[^:]+: 6e43e441 fcadd v1\.8h, v2\.8h, v3\.8h, #90
+[^:]+: 4e63d441 fadd v1\.2d, v2\.2d, v3\.2d
+[^:]+: 0e23d441 fadd v1\.2s, v2\.2s, v3\.2s
+[^:]+: 4e23d441 fadd v1\.4s, v2\.4s, v3\.4s
+[^:]+: 0e401400 fadd v0\.4h, v0\.4h, v0\.4h
+[^:]+: 0e431441 fadd v1\.4h, v2\.4h, v3\.4h
+[^:]+: 4e401400 fadd v0\.8h, v0\.8h, v0\.8h
+[^:]+: 4e431441 fadd v1\.8h, v2\.8h, v3\.8h
diff --git a/gas/testsuite/gas/aarch64/advsimd-compnum.s b/gas/testsuite/gas/aarch64/advsimd-compnum.s
new file mode 100644
index 0000000..fcf25f8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-compnum.s
@@ -0,0 +1,9 @@
+ .include "advsimd-armv8_3.s"
+
+ fadd v1.2d, v2.2d, v3.2d
+ fadd v1.2s, v2.2s, v3.2s
+ fadd v1.4s, v2.4s, v3.4s
+ fadd v0.4h, v0.4h, v0.4h
+ fadd v1.4h, v2.4h, v3.4h
+ fadd v0.8h, v0.8h, v0.8h
+ fadd v1.8h, v2.8h, v3.8h
diff --git a/include/ChangeLog b/include/ChangeLog
index f3e5811..5a4d1e1 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
+ (AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.
+
2017-02-22 Andrew Waterman <andrew@sifive.com>
* opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index c4f75e5..8dbb540 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -54,6 +54,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
+#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
@@ -72,7 +73,8 @@ typedef uint32_t aarch64_insn;
| AARCH64_FEATURE_RAS)
#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
AARCH64_FEATURE_V8_3 \
- | AARCH64_FEATURE_RCPC)
+ | AARCH64_FEATURE_RCPC \
+ | AARCH64_FEATURE_COMPNUM)
#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2bbe8b8..b680f24 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,12 @@
+2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
+ (aarch64_feature_compnum): ...this.
+ (SIMD_V8_3): Replace with...
+ (COMPNUM): ...this.
+ (CNUM_INSN): New macro.
+ (aarch64_opcode_table): Use it for the complex number instructions.
+
2017-02-24 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 472205f..705ace6 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1938,8 +1938,8 @@ static const aarch64_feature_set aarch64_feature_v8_3 =
AARCH64_FEATURE (AARCH64_FEATURE_V8_3, 0);
static const aarch64_feature_set aarch64_feature_fp_v8_3 =
AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_FP, 0);
-static const aarch64_feature_set aarch64_feature_simd_v8_3 =
- AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_SIMD, 0);
+static const aarch64_feature_set aarch64_feature_compnum =
+ AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0);
static const aarch64_feature_set aarch64_feature_rcpc =
AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0);
@@ -1959,7 +1959,7 @@ static const aarch64_feature_set aarch64_feature_rcpc =
#define SVE &aarch64_feature_sve
#define ARMV8_3 &aarch64_feature_v8_3
#define FP_V8_3 &aarch64_feature_fp_v8_3
-#define SIMD_V8_3 &aarch64_feature_simd_v8_3
+#define COMPNUM &aarch64_feature_compnum
#define RCPC &aarch64_feature_rcpc
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
@@ -1989,6 +1989,8 @@ static const aarch64_feature_set aarch64_feature_rcpc =
FLAGS | F_STRICT, TIED, NULL }
#define V8_3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, ARMV8_3, OPS, QUALS, FLAGS, 0, NULL }
+#define CNUM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS, 0, NULL }
#define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, NULL }
@@ -2130,7 +2132,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
SF16_INSN ("fmulx", 0x2f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ),
RDMA_INSN ("sqrdmlah",0x2f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
RDMA_INSN ("sqrdmlsh",0x2f00f000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
- {"fcmla", 0x2f001000, 0xbf009400, asimdelem, OP_FCMLA_ELEM, SIMD_V8_3, OP4 (Vd, Vn, Em, IMM_ROT2), QL_ELEMENT_ROT, F_SIZEQ, 0, NULL},
+ CNUM_INSN ("fcmla", 0x2f001000, 0xbf009400, asimdelem, OP_FCMLA_ELEM, OP4 (Vd, Vn, Em, IMM_ROT2), QL_ELEMENT_ROT, F_SIZEQ),
/* AdvSIMD EXT. */
SIMD_INSN ("ext", 0x2e000000, 0xbfe08400, asimdext, 0, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ),
/* AdvSIMD modified immediate. */
@@ -2374,8 +2376,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
/* AdvSIMD three same extension. */
RDMA_INSN ("sqrdmlah",0x2e008400, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ),
RDMA_INSN ("sqrdmlsh",0x2e008c00, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ),
- {"fcmla", 0x2e00c400, 0xbf20e400, asimdsame, 0, SIMD_V8_3, OP4 (Vd, Vn, Vm, IMM_ROT1), QL_V3SAMEHSD_ROT, F_SIZEQ, 0, NULL},
- {"fcadd", 0x2e00e400, 0xbf20ec00, asimdsame, 0, SIMD_V8_3, OP4 (Vd, Vn, Vm, IMM_ROT3), QL_V3SAMEHSD_ROT, F_SIZEQ, 0, NULL},
+ CNUM_INSN ("fcmla", 0x2e00c400, 0xbf20e400, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT1), QL_V3SAMEHSD_ROT, F_SIZEQ),
+ CNUM_INSN ("fcadd", 0x2e00e400, 0xbf20ec00, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT3), QL_V3SAMEHSD_ROT, F_SIZEQ),
/* AdvSIMD shift by immediate. */
SIMD_INSN ("sshr", 0xf000400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0),
SIMD_INSN ("ssra", 0xf001400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0),
generated by cgit v1.1 at 2024-09-08 12:26:59 +0000