diff options
| -rw-r--r-- | bfd/elfxx-riscv.c | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zvksg.d | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zvksg.s | 4 |
3 files changed, 19 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 5d51ef6..e2a7d8c 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1165,6 +1165,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zvks", "zvksed", check_implicit_always}, {"zvks", "zvksh", check_implicit_always}, {"zvks", "zvbb", check_implicit_always}, + {"zvksg", "zvks", check_implicit_always}, + {"zvksg", "zvkg", check_implicit_always}, {"smaia", "ssaia", check_implicit_always}, {"smstateen", "ssstateen", check_implicit_always}, {"smepmp", "zicsr", check_implicit_always}, @@ -1282,6 +1284,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zvksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvksg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, diff --git a/gas/testsuite/gas/riscv/zvksg.d b/gas/testsuite/gas/riscv/zvksg.d new file mode 100644 index 0000000..24a7126 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvksg.d @@ -0,0 +1,12 @@ +#as: -march=rv64gc_zvksg +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+86802277[ ]+vsm4k.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+ae802277[ ]+vsm3c.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+b2862277[ ]+vghsh.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+a2c8a277[ ]+vgmul.vv[ ]+v4,v12 diff --git a/gas/testsuite/gas/riscv/zvksg.s b/gas/testsuite/gas/riscv/zvksg.s new file mode 100644 index 0000000..8da053e --- /dev/null +++ b/gas/testsuite/gas/riscv/zvksg.s @@ -0,0 +1,4 @@ + vsm4k.vi v4, v8, 0 + vsm3c.vi v4, v8, 0 + vghsh.vv v4, v8, v12 + vgmul.vv v4, v12 |