diff options
| -rw-r--r-- | gas/ChangeLog | 10 | ||||
| -rw-r--r-- | gas/doc/c-bpf.texi | 20 | ||||
| -rw-r--r-- | gas/testsuite/gas/bpf/mem-be-pseudoc.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/bpf/mem-be.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/bpf/mem-pseudoc.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/bpf/mem-pseudoc.s | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/bpf/mem.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/bpf/mem.s | 4 | ||||
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/bpf.h | 3 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/bpf-opc.c | 10 |
12 files changed, 78 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 66c95a1..f91c045 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,15 @@ 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> + * testsuite/gas/bpf/mem.s: Add signed load instructions. + * testsuite/gas/bpf/mem-pseudoc.s: Likewise. + * testsuite/gas/bpf/mem.d: Likewise. + * testsuite/gas/bpf/mem-pseudoc.d: Likewise. + * testsuite/gas/bpf/mem-be.d: Likewise. + * doc/c-bpf.texi (BPF Instructions): Document the signed load + instructions. + +2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> + * testsuite/gas/bpf/alu.s: Test movs instructions. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction. diff --git a/gas/doc/c-bpf.texi b/gas/doc/c-bpf.texi index a3814e9..bebf760 100644 --- a/gas/doc/c-bpf.texi +++ b/gas/doc/c-bpf.texi @@ -483,6 +483,26 @@ Generic 16-bit load. Generic 8-bit load. @end table +Signed load to register instructions: + +@table @code +@item ldxsdw rd, [rs + offset16] +@itemx rd = *(i64 *) (rs + offset16) +Generic 64-bit signed load. + +@item ldxsw rd, [rs + offset16] +@itemx rd = *(i32 *) (rs + offset16) +Generic 32-bit signed load. + +@item ldxsh rd, [rs + offset16] +@itemx rd = *(i16 *) (rs + offset16) +Generic 16-bit signed load. + +@item ldxsb rd, [rs + offset16] +@itemx rd = *(i8 *) (rs + offset16) +Generic 8-bit signed load. +@end table + Store from register instructions: @table @code diff --git a/gas/testsuite/gas/bpf/mem-be-pseudoc.d b/gas/testsuite/gas/bpf/mem-be-pseudoc.d index ef13fe1..9a1ffc1 100644 --- a/gas/testsuite/gas/bpf/mem-be-pseudoc.d +++ b/gas/testsuite/gas/bpf/mem-be-pseudoc.d @@ -28,3 +28,7 @@ Disassembly of section .text: 88: 6a 10 7e ef 11 22 33 44 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344 90: 62 10 7e ef 11 22 33 44 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344 98: 7a 10 ff fe 11 22 33 44 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344 + a0: 81 21 7e ef 00 00 00 00 r2=\*\(i32\*\)\(r1\+0x7eef\) + a8: 89 21 7e ef 00 00 00 00 r2=\*\(i16\*\)\(r1\+0x7eef\) + b0: 91 21 7e ef 00 00 00 00 r2=\*\(i8\*\)\(r1\+0x7eef\) + b8: 99 21 7e ef 00 00 00 00 r2=\*\(i64\*\)\(r1\+0x7eef\) diff --git a/gas/testsuite/gas/bpf/mem-be.d b/gas/testsuite/gas/bpf/mem-be.d index f24efaa..5746b6a 100644 --- a/gas/testsuite/gas/bpf/mem-be.d +++ b/gas/testsuite/gas/bpf/mem-be.d @@ -28,3 +28,7 @@ Disassembly of section .text: 88: 6a 10 7e ef 11 22 33 44 sth \[%r1\+0x7eef\],0x11223344 90: 62 10 7e ef 11 22 33 44 stw \[%r1\+0x7eef\],0x11223344 98: 7a 10 ff fe 11 22 33 44 stdw \[%r1\+0xfffe\],0x11223344 + a0: 81 21 7e ef 00 00 00 00 ldxsw %r2,\[%r1\+0x7eef\] + a8: 89 21 7e ef 00 00 00 00 ldxsh %r2,\[%r1\+0x7eef\] + b0: 91 21 7e ef 00 00 00 00 ldxsb %r2,\[%r1\+0x7eef\] + b8: 99 21 7e ef 00 00 00 00 ldxsdw %r2,\[%r1\+0x7eef\]
\ No newline at end of file diff --git a/gas/testsuite/gas/bpf/mem-pseudoc.d b/gas/testsuite/gas/bpf/mem-pseudoc.d index 4e8b7d0..8481048 100644 --- a/gas/testsuite/gas/bpf/mem-pseudoc.d +++ b/gas/testsuite/gas/bpf/mem-pseudoc.d @@ -28,3 +28,7 @@ Disassembly of section .text: 88: 6a 01 ef 7e 44 33 22 11 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344 90: 62 01 ef 7e 44 33 22 11 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344 98: 7a 01 fe ff 44 33 22 11 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344 + a0: 81 12 ef 7e 00 00 00 00 r2=\*\(i32\*\)\(r1\+0x7eef\) + a8: 89 12 ef 7e 00 00 00 00 r2=\*\(i16\*\)\(r1\+0x7eef\) + b0: 91 12 ef 7e 00 00 00 00 r2=\*\(i8\*\)\(r1\+0x7eef\) + b8: 99 12 ef 7e 00 00 00 00 r2=\*\(i64\*\)\(r1\+0x7eef\) diff --git a/gas/testsuite/gas/bpf/mem-pseudoc.s b/gas/testsuite/gas/bpf/mem-pseudoc.s index 7b8c832..1ffa2e2 100644 --- a/gas/testsuite/gas/bpf/mem-pseudoc.s +++ b/gas/testsuite/gas/bpf/mem-pseudoc.s @@ -21,3 +21,7 @@ *(u16 *)(r1 + 0x7eef) = 0x11223344 *(u32 *)(r1 + 0x7eef) = 0x11223344 *(u64 *)(r1 + -2) = 0x11223344 + r2 = *(i32*)(r1+0x7eef) + r2 = *(i16*)(r1+0x7eef) + r2 = *(i8*)(r1+0x7eef) + r2 = *(i64*)(r1+0x7eef) diff --git a/gas/testsuite/gas/bpf/mem.d b/gas/testsuite/gas/bpf/mem.d index 669aae3..8b7a488 100644 --- a/gas/testsuite/gas/bpf/mem.d +++ b/gas/testsuite/gas/bpf/mem.d @@ -28,3 +28,7 @@ Disassembly of section .text: 88: 6a 01 ef 7e 44 33 22 11 sth \[%r1\+0x7eef\],0x11223344 90: 62 01 ef 7e 44 33 22 11 stw \[%r1\+0x7eef\],0x11223344 98: 7a 01 fe ff 44 33 22 11 stdw \[%r1\+0xfffe\],0x11223344 + a0: 81 12 ef 7e 00 00 00 00 ldxsw %r2,\[%r1\+0x7eef\] + a8: 89 12 ef 7e 00 00 00 00 ldxsh %r2,\[%r1\+0x7eef\] + b0: 91 12 ef 7e 00 00 00 00 ldxsb %r2,\[%r1\+0x7eef\] + b8: 99 12 ef 7e 00 00 00 00 ldxsdw %r2,\[%r1\+0x7eef\]
\ No newline at end of file diff --git a/gas/testsuite/gas/bpf/mem.s b/gas/testsuite/gas/bpf/mem.s index 798a18e..6323cf1 100644 --- a/gas/testsuite/gas/bpf/mem.s +++ b/gas/testsuite/gas/bpf/mem.s @@ -22,3 +22,7 @@ sth [%r1+0x7eef], 0x11223344 stw [%r1+0x7eef], 0x11223344 stdw [%r1-2], 0x11223344 + ldxsw %r2, [%r1+0x7eef] + ldxsh %r2, [%r1+0x7eef] + ldxsb %r2, [%r1+0x7eef] + ldxsdw %r2, [%r1+0x7eef] diff --git a/include/ChangeLog b/include/ChangeLog index 5872f28..ccf1661 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,11 @@ 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> + * opcode/bpf.h (enum bpf_insn_id): Add entries for signed load + instructions. + (BPF_MODE_SMEM): Define. + +2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> + * opcode/bpf.h (BPF_OFFSET16_MOVS8): Define. (BPF_OFFSET16_MOVS16): Likewise. (BPF_OFFSET16_MOVS32): Likewise. diff --git a/include/opcode/bpf.h b/include/opcode/bpf.h index 48f06c2..a491df6 100644 --- a/include/opcode/bpf.h +++ b/include/opcode/bpf.h @@ -112,6 +112,7 @@ typedef uint64_t bpf_insn_word; #define BPF_MODE_IND ((uint64_t)0x40 << 56) #define BPF_MODE_MEM ((uint64_t)0x60 << 56) #define BPF_MODE_ATOMIC ((uint64_t)0xc0 << 56) +#define BPF_MODE_SMEM ((uint64_t)0x80 << 56) #define BPF_SIZE_W ((uint64_t)0x00 << 56) #define BPF_SIZE_H ((uint64_t)0x08 << 56) @@ -186,6 +187,8 @@ enum bpf_insn_id BPF_INSN_LDINDB, BPF_INSN_LDINDH, BPF_INSN_LDINDW, BPF_INSN_LDINDDW, /* Generic load instructions (to register.) */ BPF_INSN_LDXB, BPF_INSN_LDXH, BPF_INSN_LDXW, BPF_INSN_LDXDW, + /* Generic signed load instructions. */ + BPF_INSN_LDXSB, BPF_INSN_LDXSH, BPF_INSN_LDXSW, BPF_INSN_LDXSDW, /* Generic store instructions (from register.) */ BPF_INSN_STXBR, BPF_INSN_STXHR, BPF_INSN_STXWR, BPF_INSN_STXDWR, BPF_INSN_STXBI, BPF_INSN_STXHI, BPF_INSN_STXWI, BPF_INSN_STXDWI, diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 55d4e7d..f88e9c8 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> + * bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW} + instructions. + +2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> + * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R instructions. and MOVS32I instructions. diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c index 72be1d9..efd3257 100644 --- a/opcodes/bpf-opc.c +++ b/opcodes/bpf-opc.c @@ -217,6 +217,16 @@ const struct bpf_opcode bpf_opcodes[] = {BPF_INSN_LDXDW, "ldxdw%W%dr , [ %sr %o16 ]","%dr = * ( u64 * ) ( %sr %o16 )", BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_DW|BPF_MODE_MEM}, + /* Generic signed load instructions (to register.) */ + {BPF_INSN_LDXSB, "ldxsb%W%dr , [ %sr %o16 ]", "%dr = * ( i8 * ) ( %sr %o16 )", + BPF_V4, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_B|BPF_MODE_SMEM}, + {BPF_INSN_LDXSH, "ldxsh%W%dr , [ %sr %o16 ]", "%dr = * ( i16 * ) ( %sr %o16 )", + BPF_V4, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_H|BPF_MODE_SMEM}, + {BPF_INSN_LDXSW, "ldxsw%W%dr , [ %sr %o16 ]", "%dr = * ( i32 * ) ( %sr %o16 )", + BPF_V4, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_W|BPF_MODE_SMEM}, + {BPF_INSN_LDXSDW, "ldxsdw%W%dr , [ %sr %o16 ]","%dr = * ( i64 * ) ( %sr %o16 )", + BPF_V4, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_DW|BPF_MODE_SMEM}, + /* Generic store instructions (from register.) */ {BPF_INSN_STXBR, "stxb%W[ %dr %o16 ] , %sr", "* ( u8 * ) ( %dr %o16 ) = %sr", BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_B|BPF_MODE_MEM}, |