diff options
| -rw-r--r-- | sim/mips/cp1.c | 3 | ||||
| -rw-r--r-- | sim/mips/dsp.igen | 2 | ||||
| -rw-r--r-- | sim/mips/dsp2.igen | 5 | ||||
| -rw-r--r-- | sim/mips/interp.c | 2 | ||||
| -rw-r--r-- | sim/mips/mips.igen | 21 |
5 files changed, 12 insertions, 21 deletions
diff --git a/sim/mips/cp1.c b/sim/mips/cp1.c index aa8b05a..3e2d5d9 100644 --- a/sim/mips/cp1.c +++ b/sim/mips/cp1.c @@ -630,7 +630,6 @@ fp_rint (sim_cpu *cpu, FP_formats fmt) { sim_fpu wop = {0}, wtemp = {0}, wmagic = {0}, wans = {0}; - int64_t intermediate; int status = 0; sim_fpu_round round = rounding_mode (GETRM()); @@ -743,7 +742,6 @@ fp_r6_cmp (sim_cpu *cpu, { sim_fpu wop1, wop2; int result = 0; - int signalling = cond & 0x8; switch (fmt) { @@ -1556,7 +1554,6 @@ fpu_inv1(sim_fpu *f, const sim_fpu *l) sim_fpu_class_number, 0, IMPLICIT_1, 0 }; int status = 0; - sim_fpu t; if (sim_fpu_is_zero (l)) { diff --git a/sim/mips/dsp.igen b/sim/mips/dsp.igen index 5f60194..d825e2d 100644 --- a/sim/mips/dsp.igen +++ b/sim/mips/dsp.igen @@ -66,7 +66,6 @@ int32_t h1, h2; uint32_t v1 = GPR[rs]; uint32_t v2 = GPR[rt]; - uint32_t result = 0; h1 = (int32_t)v1; h2 = (int32_t)v2; if (op == 0) // ADD @@ -1888,7 +1887,6 @@ :function:::void:do_h_extr:int rt, int ac, int shift { - int i; uint32_t lo = DSPLO(ac); uint32_t hi = DSPHI(ac); uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo; diff --git a/sim/mips/dsp2.igen b/sim/mips/dsp2.igen index 4fd5880..3c6e4b2 100644 --- a/sim/mips/dsp2.igen +++ b/sim/mips/dsp2.igen @@ -195,7 +195,7 @@ // round: 0 = no rounding, 1 = rounding :function:::void:do_qb_shra:int rd, int rt, int shift, int round { - int i, j; + int i; int8_t q0; uint32_t v1 = GPR[rt]; uint32_t result = 0; @@ -216,7 +216,7 @@ :function:::void:do_ph_shrl:int rd, int rt, int shift { - int i, j; + int i; uint16_t h0; uint32_t v1 = GPR[rt]; uint32_t result = 0; @@ -260,7 +260,6 @@ // round: 0 = no rounding, 1 = rounding :function:::void:do_qh_w_op:int rd, int rs, int rt, int op, int round { - int i; int64_t v0; int32_t v1 = (int32_t)GPR[rs]; int32_t v2 = (int32_t)GPR[rt]; diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 18ccef8..cb650a5 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -400,8 +400,6 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb, /* If we find an entry at address 0, then we will end up allocating a new buffer in the "memory alias" command below. The region at address 0 will be deleted. */ - address_word size = (entry->modulo != 0 - ? entry->modulo : entry->nr_bytes); if (entry->addr == 0 && (!match || entry->level < match->level)) match = entry; diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 0746a52..09f82aa 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -1133,18 +1133,17 @@ :function:::void:do_pref:int hint, int insn_offset, int insn_base { + /* address_word base = GPR[insn_base]; address_word offset = EXTEND16 (insn_offset); - { - address_word vaddr = loadstore_ea (SD_, base, offset); - address_word paddr = vaddr; - /* Prefetch (paddr, vaddr, isDATA, hint); */ - } + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr = vaddr; + Prefetch (paddr, vaddr, isDATA, hint); + */ } :function:::void:do_sc:int rt, int offsetarg, int basereg, address_word instruction_0, int store_ll_bit { - uint32_t instruction = instruction_0; address_word base = GPR[basereg]; address_word offset = EXTEND16 (offsetarg); { @@ -1684,13 +1683,13 @@ :function:::void:do_prefx:int hint, int rindex, int rbase { + /* address_word base = GPR[rbase]; address_word index = GPR[rindex]; - { - address_word vaddr = loadstore_ea (SD_, base, index); - address_word paddr = vaddr; - /* Prefetch (paddr, vaddr, isDATA, hint); */ - } + address_word vaddr = loadstore_ea (SD_, base, index); + address_word paddr = vaddr; + Prefetch (paddr, vaddr, isDATA, hint); + */ } :function:::void:do_sdc1:int ft, int offset, int base |