aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--bfd/ChangeLog7
-rw-r--r--bfd/elf64-ppc.c34
-rw-r--r--ld/ChangeLog6
-rw-r--r--ld/testsuite/ld-powerpc/elfv2exe.d2
-rw-r--r--ld/testsuite/ld-powerpc/elfv2so.d12
5 files changed, 38 insertions, 23 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 964ab71..0914e7d 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,5 +1,12 @@
2019-06-23 Alan Modra <amodra@gmail.com>
+ PR 24704
+ * elf64-ppc.c (R_PPC64_GOT16_DS): Don't set has_gotrel.
+ (ppc64_elf_edit_toc): Don't remove R_PPC64_GOT16_DS got entries.
+ Reduce range of offsets allowed for other GOT relocs.
+
+2019-06-23 Alan Modra <amodra@gmail.com>
+
PR 24689
* elfcode.h (elf_object_p): Warning fix.
diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c
index 6162019..c5c18d0 100644
--- a/bfd/elf64-ppc.c
+++ b/bfd/elf64-ppc.c
@@ -4610,7 +4610,6 @@ ppc64_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
sec->has_tls_reloc = 1;
goto dogot;
- case R_PPC64_GOT16_DS:
case R_PPC64_GOT16_HA:
case R_PPC64_GOT16_LO_DS:
case R_PPC64_GOT_PCREL34:
@@ -4618,6 +4617,7 @@ ppc64_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
ppc64_elf_section_data (sec)->has_gotrel = 1;
/* Fall through. */
+ case R_PPC64_GOT16_DS:
case R_PPC64_GOT16:
case R_PPC64_GOT16_HI:
case R_PPC64_GOT16_LO:
@@ -9010,10 +9010,15 @@ ppc64_elf_edit_toc (struct bfd_link_info *info)
r_type = ELF64_R_TYPE (rel->r_info);
switch (r_type)
{
+ /* Note that we don't delete GOT entries for
+ R_PPC64_GOT16_DS since we'd need a lot more
+ analysis. For starters, the preliminary layout is
+ before the GOT, PLT, dynamic sections and stubs are
+ laid out. Then we'd need to allow for changes in
+ distance between sections caused by alignment. */
default:
continue;
- case R_PPC64_GOT16_DS:
case R_PPC64_GOT16_HA:
case R_PPC64_GOT16_LO_DS:
sym_addend = rel->r_addend;
@@ -9039,24 +9044,18 @@ ppc64_elf_edit_toc (struct bfd_link_info *info)
val += sym_addend;
val += sym_sec->output_section->vma + sym_sec->output_offset;
+/* Fudge factor to allow for the fact that the preliminary layout
+ isn't exact. Reduce limits by this factor. */
+#define LIMIT_ADJUST(LIMIT) ((LIMIT) - (LIMIT) / 16)
+
switch (r_type)
{
default:
continue;
- case R_PPC64_GOT16_DS:
- if (val - got + 0x8000 >= 0x10000)
- continue;
- if (!bfd_get_section_contents (ibfd, sec, buf,
- rel->r_offset & ~3, 4))
- goto got_error_ret;
- insn = bfd_get_32 (ibfd, buf);
- if ((insn & (0x3f << 26 | 0x3)) != 58u << 26 /* ld */)
- continue;
- break;
-
case R_PPC64_GOT16_HA:
- if (val - got + 0x80008000ULL >= 0x100000000ULL)
+ if (val - got + LIMIT_ADJUST (0x80008000ULL)
+ >= LIMIT_ADJUST (0x100000000ULL))
continue;
if (!bfd_get_section_contents (ibfd, sec, buf,
@@ -9069,7 +9068,8 @@ ppc64_elf_edit_toc (struct bfd_link_info *info)
break;
case R_PPC64_GOT16_LO_DS:
- if (val - got + 0x80008000ULL >= 0x100000000ULL)
+ if (val - got + LIMIT_ADJUST (0x80008000ULL)
+ >= LIMIT_ADJUST (0x100000000ULL))
continue;
if (!bfd_get_section_contents (ibfd, sec, buf,
rel->r_offset & ~3, 4))
@@ -9082,7 +9082,8 @@ ppc64_elf_edit_toc (struct bfd_link_info *info)
case R_PPC64_GOT_PCREL34:
pc = rel->r_offset;
pc += sec->output_section->vma + sec->output_offset;
- if (val - pc + (1ULL << 33) >= 1ULL << 34)
+ if (val - pc + LIMIT_ADJUST (1ULL << 33)
+ >= LIMIT_ADJUST (1ULL << 34))
continue;
if (!bfd_get_section_contents (ibfd, sec, buf,
rel->r_offset & ~3, 8))
@@ -9095,6 +9096,7 @@ ppc64_elf_edit_toc (struct bfd_link_info *info)
continue;
break;
}
+#undef LIMIT_ADJUST
if (h != NULL)
ent = h->got.glist;
diff --git a/ld/ChangeLog b/ld/ChangeLog
index e5c85e1..6dcfe30 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,9 @@
+2019-06-23 Alan Modra <amodra@gmail.com>
+
+ PR 24704
+ * testsuite/ld-powerpc/elfv2exe.d: Update.
+ * testsuite/ld-powerpc/elfv2so.d: Update.
+
2019-06-14 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/ld-aarch64/aarch64-elf.exp: Add emit-relocs-22 and -23.
diff --git a/ld/testsuite/ld-powerpc/elfv2exe.d b/ld/testsuite/ld-powerpc/elfv2exe.d
index 769f846..0ccfcbf 100644
--- a/ld/testsuite/ld-powerpc/elfv2exe.d
+++ b/ld/testsuite/ld-powerpc/elfv2exe.d
@@ -34,7 +34,7 @@ Disassembly of section \.text:
.*: (e8 62 80 08|08 80 62 e8) ld r3,-32760\(r2\)
.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_branch\.f2>
.*: (60 00 00 00|00 00 00 60) nop
-.*: (38 62 80 10|10 80 62 38) addi r3,r2,-32752
+.*: (38 62 80 18|18 80 62 38) addi r3,r2,-32744
.*: (48 .. .. ..|.. .. .. 48) bl 10008888 <f3>
.*: (60 00 00 00|00 00 00 60) nop
.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_branch\.f4>
diff --git a/ld/testsuite/ld-powerpc/elfv2so.d b/ld/testsuite/ld-powerpc/elfv2so.d
index 081eb49..0162bd0 100644
--- a/ld/testsuite/ld-powerpc/elfv2so.d
+++ b/ld/testsuite/ld-powerpc/elfv2so.d
@@ -9,35 +9,35 @@ Disassembly of section \.text:
.* <.*\.plt_call\.f4>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
-.*: (e9 82 80 38|38 80 82 e9) ld r12,-32712\(r2\)
+.*: (e9 82 80 40|40 80 82 e9) ld r12,-32704\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
\.\.\.
.* <.*\.plt_call\.f3>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
-.*: (e9 82 80 28|28 80 82 e9) ld r12,-32728\(r2\)
+.*: (e9 82 80 30|30 80 82 e9) ld r12,-32720\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
\.\.\.
.* <.*\.plt_call\.f5>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
-.*: (e9 82 80 20|20 80 82 e9) ld r12,-32736\(r2\)
+.*: (e9 82 80 28|28 80 82 e9) ld r12,-32728\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
\.\.\.
.* <.*\.plt_call\.f1>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
-.*: (e9 82 80 40|40 80 82 e9) ld r12,-32704\(r2\)
+.*: (e9 82 80 48|48 80 82 e9) ld r12,-32696\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
\.\.\.
.* <.*\.plt_call\.f2>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
-.*: (e9 82 80 30|30 80 82 e9) ld r12,-32720\(r2\)
+.*: (e9 82 80 38|38 80 82 e9) ld r12,-32712\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
\.\.\.
@@ -52,7 +52,7 @@ Disassembly of section \.text:
.*: (e8 62 80 08|08 80 62 e8) ld r3,-32760\(r2\)
.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f2>
.*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\)
-.*: (38 62 80 48|48 80 62 38) addi r3,r2,-32696
+.*: (38 62 80 50|50 80 62 38) addi r3,r2,-32688
.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f3>
.*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\)
.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f4>
generated by cgit v1.1 at 2024-11-14 14:56:14 +0000