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-rw-r--r--gas/testsuite/ChangeLog5
-rw-r--r--gas/testsuite/gas/mips/loongson-3a.d111
-rw-r--r--gas/testsuite/gas/mips/loongson-3a.s105
-rw-r--r--gas/testsuite/gas/mips/mips.exp2
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/mips-opc.c56
6 files changed, 262 insertions, 22 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 3675cbc2..8b4e801 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2010-12-11 Mingming Sun <mingm.sun@gmail.com>
+
+ * gas/mips/loongson-3a.s, gas/mips/loongson-3a.d: New test.
+ * gas/mips/mips.exp: Run it.
+
2010-12-09 Maciej W. Rozycki <macro@codesourcery.com>
* gas/mips/elf_ase_mips16.d: Update test for new MIPS16 ASE flag
diff --git a/gas/testsuite/gas/mips/loongson-3a.d b/gas/testsuite/gas/mips/loongson-3a.d
new file mode 100644
index 0000000..f0eb0e3
--- /dev/null
+++ b/gas/testsuite/gas/mips/loongson-3a.d
@@ -0,0 +1,111 @@
+#as: -march=loongson3a -mabi=o64
+#objdump: -M reg-names=numeric -dr
+#name: Loongson-3A tests
+
+.*: file format .*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <movz_insns>:
+.*: 0064100b movn \$2,\$3,\$4
+
+[0-9a-f]+ <integer_insns>:
+.*: 70641010 gsmult \$2,\$3,\$4
+.*: 70c72812 gsmultu \$5,\$6,\$7
+.*: 712a4011 gsdmult \$8,\$9,\$10
+.*: 718d5813 gsdmultu \$11,\$12,\$13
+.*: 71f07014 gsdiv \$14,\$15,\$16
+.*: 72538816 gsdivu \$17,\$18,\$19
+.*: 72b6a015 gsddiv \$20,\$21,\$22
+.*: 7319b817 gsddivu \$23,\$24,\$25
+.*: 737cd01c gsmod \$26,\$27,\$28
+.*: 73dfe81e gsmodu \$29,\$30,\$31
+.*: 7064101d gsdmod \$2,\$3,\$4
+.*: 70c7281f gsdmodu \$5,\$6,\$7
+
+[0-9a-f]+ <simd_insns>:
+.*: 4b420802 packsshb \$f0,\$f1,\$f2
+.*: 4b2520c2 packsswh \$f3,\$f4,\$f5
+.*: 4b683982 packushb \$f6,\$f7,\$f8
+.*: 4bcb5240 paddb \$f9,\$f10,\$f11
+.*: 4b4e6b00 paddh \$f12,\$f13,\$f14
+.*: 4b7183c0 paddw \$f15,\$f16,\$f17
+.*: 4bf49c80 paddd \$f18,\$f19,\$f20
+.*: 4b97b540 paddsb \$f21,\$f22,\$f23
+.*: 4b1ace00 paddsh \$f24,\$f25,\$f26
+.*: 4bbde6c0 paddusb \$f27,\$f28,\$f29
+.*: 4b220800 paddush \$f0,\$f1,\$f2
+.*: 4be520c2 pandn \$f3,\$f4,\$f5
+.*: 4b283988 pavgb \$f6,\$f7,\$f8
+.*: 4b0b5248 pavgh \$f9,\$f10,\$f11
+.*: 4b8e6b09 pcmpeqb \$f12,\$f13,\$f14
+.*: 4b5183c9 pcmpeqh \$f15,\$f16,\$f17
+.*: 4b149c89 pcmpeqw \$f18,\$f19,\$f20
+.*: 4bb7b549 pcmpgtb \$f21,\$f22,\$f23
+.*: 4b7ace09 pcmpgth \$f24,\$f25,\$f26
+.*: 4b3de6c9 pcmpgtw \$f27,\$f28,\$f29
+.*: 4b42080e pextrh \$f0,\$f1,\$f2
+.*: 4b8520c3 pinsrh_0 \$f3,\$f4,\$f5
+.*: 4ba83983 pinsrh_1 \$f6,\$f7,\$f8
+.*: 4bcb5243 pinsrh_2 \$f9,\$f10,\$f11
+.*: 4bee6b03 pinsrh_3 \$f12,\$f13,\$f14
+.*: 4b7183ce pmaddhw \$f15,\$f16,\$f17
+.*: 4b549c88 pmaxsh \$f18,\$f19,\$f20
+.*: 4b97b548 pmaxub \$f21,\$f22,\$f23
+.*: 4b7ace08 pminsh \$f24,\$f25,\$f26
+.*: 4bbde6c8 pminub \$f27,\$f28,\$f29
+.*: 4ba0080f pmovmskb \$f0,\$f1
+.*: 4ba4188a pmulhuh \$f2,\$f3,\$f4
+.*: 4b67314a pmulhh \$f5,\$f6,\$f7
+.*: 4b4a4a0a pmullh \$f8,\$f9,\$f10
+.*: 4b8d62ca pmuluw \$f11,\$f12,\$f13
+.*: 4b307b8d pasubub \$f14,\$f15,\$f16
+.*: 4b80944f biadd \$f17,\$f18
+.*: 4b15a4c2 pshufh \$f19,\$f20,\$f21
+.*: 4b38bd8a psllh \$f22,\$f23,\$f24
+.*: 4b1bd64a psllw \$f25,\$f26,\$f27
+.*: 4b7eef0b psrah \$f28,\$f29,\$f30
+.*: 4b42080b psraw \$f0,\$f1,\$f2
+.*: 4b2520cb psrlh \$f3,\$f4,\$f5
+.*: 4b08398b psrlw \$f6,\$f7,\$f8
+.*: 4bcb5241 psubb \$f9,\$f10,\$f11
+.*: 4b4e6b01 psubh \$f12,\$f13,\$f14
+.*: 4b7183c1 psubw \$f15,\$f16,\$f17
+.*: 4bf49c81 psubd \$f18,\$f19,\$f20
+.*: 4b97b541 psubsb \$f21,\$f22,\$f23
+.*: 4b1ace01 psubsh \$f24,\$f25,\$f26
+.*: 4bbde6c1 psubusb \$f27,\$f28,\$f29
+.*: 4b220801 psubush \$f0,\$f1,\$f2
+.*: 4b6520c3 punpckhbh \$f3,\$f4,\$f5
+.*: 4b283983 punpckhhw \$f6,\$f7,\$f8
+.*: 4bab524b punpckhwd \$f9,\$f10,\$f11
+.*: 4b4e6b03 punpcklbh \$f12,\$f13,\$f14
+.*: 4b1183c3 punpcklhw \$f15,\$f16,\$f17
+.*: 4b949c8b punpcklwd \$f18,\$f19,\$f20
+
+[0-9a-f]+ <fixed_point_insns>:
+.*: 4b42080c add \$f0,\$f1,\$f2
+.*: 4b0520cc addu \$f3,\$f4,\$f5
+.*: 4b68398c dadd \$f6,\$f7,\$f8
+.*: 4b4b524d sub \$f9,\$f10,\$f11
+.*: 4b0e6b0d subu \$f12,\$f13,\$f14
+.*: 4b7183cd dsub \$f15,\$f16,\$f17
+.*: 4b349c8c or \$f18,\$f19,\$f20
+.*: 4b17b54e sll \$f21,\$f22,\$f23
+.*: 4b3ace0e dsll \$f24,\$f25,\$f26
+.*: 4b9de6c2 xor \$f27,\$f28,\$f29
+.*: 4ba20802 nor \$f0,\$f1,\$f2
+.*: 4bc520c2 and \$f3,\$f4,\$f5
+.*: 4b08398f srl \$f6,\$f7,\$f8
+.*: 4b2b524f dsrl \$f9,\$f10,\$f11
+.*: 4b4e6b0f sra \$f12,\$f13,\$f14
+.*: 4b7183cf dsra \$f15,\$f16,\$f17
+.*: 4b93900c sequ \$f18,\$f19
+.*: 4b95a00d sltu \$f20,\$f21
+.*: 4b97b00e sleu \$f22,\$f23
+.*: 4bb9c00c seq \$f24,\$f25
+.*: 4bbbd00d slt \$f26,\$f27
+.*: 4bbde00e sle \$f28,\$f29
+#pass
+
+
diff --git a/gas/testsuite/gas/mips/loongson-3a.s b/gas/testsuite/gas/mips/loongson-3a.s
new file mode 100644
index 0000000..73c00c0
--- /dev/null
+++ b/gas/testsuite/gas/mips/loongson-3a.s
@@ -0,0 +1,105 @@
+ .text
+ .set noreorder
+
+movz_insns:
+ movnz $2, $3, $4
+
+integer_insns:
+ gsmult $2, $3, $4
+ gsmultu $5, $6, $7
+ gsdmult $8, $9, $10
+ gsdmultu $11, $12, $13
+ gsdiv $14, $15, $16
+ gsdivu $17, $18, $19
+ gsddiv $20, $21, $22
+ gsddivu $23, $24, $25
+ gsmod $26, $27, $28
+ gsmodu $29, $30, $31
+ gsdmod $2, $3, $4
+ gsdmodu $5, $6, $7
+
+simd_insns:
+ packsshb $f0, $f1, $f2
+ packsswh $f3, $f4, $f5
+ packushb $f6, $f7, $f8
+ paddb $f9, $f10, $f11
+ paddh $f12, $f13, $f14
+ paddw $f15, $f16, $f17
+ paddd $f18, $f19, $f20
+ paddsb $f21, $f22, $f23
+ paddsh $f24, $f25, $f26
+ paddusb $f27, $f28, $f29
+ paddush $f0, $f1, $f2
+ pandn $f3, $f4, $f5
+ pavgb $f6, $f7, $f8
+ pavgh $f9, $f10, $f11
+ pcmpeqb $f12, $f13, $f14
+ pcmpeqh $f15, $f16, $f17
+ pcmpeqw $f18, $f19, $f20
+ pcmpgtb $f21, $f22, $f23
+ pcmpgth $f24, $f25, $f26
+ pcmpgtw $f27, $f28, $f29
+ pextrh $f0, $f1, $f2
+ pinsrh_0 $f3, $f4, $f5
+ pinsrh_1 $f6, $f7, $f8
+ pinsrh_2 $f9, $f10, $f11
+ pinsrh_3 $f12, $f13, $f14
+ pmaddhw $f15, $f16, $f17
+ pmaxsh $f18, $f19, $f20
+ pmaxub $f21, $f22, $f23
+ pminsh $f24, $f25, $f26
+ pminub $f27, $f28, $f29
+ pmovmskb $f0, $f1
+ pmulhuh $f2, $f3, $f4
+ pmulhh $f5, $f6, $f7
+ pmullh $f8, $f9, $f10
+ pmuluw $f11, $f12, $f13
+ pasubub $f14, $f15, $f16
+ biadd $f17, $f18
+ pshufh $f19, $f20, $f21
+ psllh $f22, $f23, $f24
+ psllw $f25, $f26, $f27
+ psrah $f28, $f29, $f30
+ psraw $f0, $f1, $f2
+ psrlh $f3, $f4, $f5
+ psrlw $f6, $f7, $f8
+ psubb $f9, $f10, $f11
+ psubh $f12, $f13, $f14
+ psubw $f15, $f16, $f17
+ psubd $f18, $f19, $f20
+ psubsb $f21, $f22, $f23
+ psubsh $f24, $f25, $f26
+ psubusb $f27, $f28, $f29
+ psubush $f0, $f1, $f2
+ punpckhbh $f3, $f4, $f5
+ punpckhhw $f6, $f7, $f8
+ punpckhwd $f9, $f10, $f11
+ punpcklbh $f12, $f13, $f14
+ punpcklhw $f15, $f16, $f17
+ punpcklwd $f18, $f19, $f20
+
+fixed_point_insns:
+ add $f0, $f1, $f2
+ addu $f3, $f4, $f5
+ dadd $f6, $f7, $f8
+ sub $f9, $f10, $f11
+ subu $f12, $f13, $f14
+ dsub $f15, $f16, $f17
+ or $f18, $f19, $f20
+ sll $f21, $f22, $f23
+ dsll $f24, $f25, $f26
+ xor $f27, $f28, $f29
+ nor $f0, $f1, $f2
+ and $f3, $f4, $f5
+ srl $f6, $f7, $f8
+ dsrl $f9, $f10, $f11
+ sra $f12, $f13, $f14
+ dsra $f15, $f16, $f17
+ sequ $f18, $f19
+ sltu $f20, $f21
+ sleu $f22, $f23
+ seq $f24, $f25
+ slt $f26, $f27
+ sle $f28, $f29
+
+
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 7075f9d..baea397 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -915,6 +915,8 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "loongson-2f-2"
run_dump_test "loongson-2f-3"
+ run_dump_test "loongson-3a"
+
run_dump_test_arches "octeon" [mips_arch_list_matching octeon]
run_list_test_arches "octeon-ill" "" \
[mips_arch_list_matching octeon]
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 844d80a..bef474e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2010-12-11 Mingming Sun <mingm.sun@gmail.com>
+
+ * mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and
+ fixed point instructions.
+
2010-12-09 Mike Frysinger <vapier@gentoo.org>
* .gitignore: New file.
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 0fa86c6..e22c20c 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -207,7 +207,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
{"add", "D,S,T", 0x45c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E },
-{"add", "D,S,T", 0x4b40000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F },
+{"add", "D,S,T", 0x4b40000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A },
{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
@@ -227,7 +227,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 },
{"addu", "D,S,T", 0x45800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E },
-{"addu", "D,S,T", 0x4b00000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F },
+{"addu", "D,S,T", 0x4b00000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A },
{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 },
{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
@@ -237,7 +237,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 },
{"and", "D,S,T", 0x47c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"and", "D,S,T", 0x4bc00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"and", "D,S,T", 0x4bc00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -553,7 +553,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 },
{"dadd", "D,S,T", 0x45e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 },
{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 },
{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
@@ -670,25 +670,25 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */
{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 },
{"dsll", "D,S,T", 0x45a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"dsll", "D,S,T", 0x4b20000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"dsll", "D,S,T", 0x4b20000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 },
{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */
{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */
{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 },
{"dsra", "D,S,T", 0x45e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"dsra", "D,S,T", 0x4b60000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"dsra", "D,S,T", 0x4b60000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 },
{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */
{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */
{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 },
{"dsrl", "D,S,T", 0x45a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 },
{"dsub", "D,S,T", 0x45e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"dsub", "D,S,T", 0x4b60000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"dsub", "D,S,T", 0x4b60000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 },
@@ -902,7 +902,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 },
{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33 },
{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F },
-{"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL2E|IL2F },
+{"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL2E|IL2F|IL3A },
{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 },
{"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
@@ -1071,7 +1071,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 },
{"nor", "D,S,T", 0x47a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"nor", "D,S,T", 0x4ba00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"nor", "D,S,T", 0x4ba00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -1081,7 +1081,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 },
{"or", "D,S,T", 0x45a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"or", "D,S,T", 0x4b20000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"or", "D,S,T", 0x4b20000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -1208,7 +1208,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 },
{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 },
{"seq", "S,T", 0x46a00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E },
-{"seq", "S,T", 0x4ba0000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F },
+{"seq", "S,T", 0x4ba0000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A },
{"seqi", "t,r,+Q", 0x7000002e, 0xfc00003f, WR_t|RD_s, 0, IOCT },
{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 },
{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 },
@@ -1237,16 +1237,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 },
{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 },
{"sle", "S,T", 0x46a0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E },
-{"sle", "S,T", 0x4ba0000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F },
+{"sle", "S,T", 0x4ba0000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A },
{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 },
{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 },
{"sleu", "S,T", 0x4680003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E },
-{"sleu", "S,T", 0x4b80000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F },
+{"sleu", "S,T", 0x4b80000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A },
{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */
{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 },
{"sll", "D,S,T", 0x45800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"sll", "D,S,T", 0x4b00000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"sll", "D,S,T", 0x4b00000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
{"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -1254,13 +1254,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 },
{"slt", "S,T", 0x46a0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E },
-{"slt", "S,T", 0x4ba0000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F },
+{"slt", "S,T", 0x4ba0000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A },
{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 },
{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 },
{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 },
{"sltu", "S,T", 0x4680003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E },
-{"sltu", "S,T", 0x4b80000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F },
+{"sltu", "S,T", 0x4b80000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A },
{"sne", "d,v,t", 0x7000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 },
{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 },
@@ -1272,13 +1272,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */
{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 },
{"sra", "D,S,T", 0x45c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"sra", "D,S,T", 0x4b40000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"sra", "D,S,T", 0x4b40000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */
{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 },
{"srl", "D,S,T", 0x45800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"srl", "D,S,T", 0x4b00000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"srl", "D,S,T", 0x4b00000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
{"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -1288,7 +1288,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 },
{"sub", "D,S,T", 0x45c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E },
-{"sub", "D,S,T", 0x4b40000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F },
+{"sub", "D,S,T", 0x4b40000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A },
{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
{"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
@@ -1305,7 +1305,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 },
{"subu", "D,S,T", 0x45800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E },
-{"subu", "D,S,T", 0x4b00000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F },
+{"subu", "D,S,T", 0x4b00000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A },
{"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 },
{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I5_33|N55},
{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
@@ -1423,7 +1423,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
{"xor", "D,S,T", 0x47800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"xor", "D,S,T", 0x4b800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"xor", "D,S,T", 0x4b800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -1838,28 +1838,40 @@ const struct mips_opcode mips_builtin_opcodes[] =
/* ST Microelectronics Loongson-2E and -2F. */
{"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsmultu", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdmult", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdmultu", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"div.g", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdiv", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdivu", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsddiv", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsddivu", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsmod", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsmodu", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdmod", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdmodu", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"packsshb", "D,S,T", 0x47400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
{"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"packsswh", "D,S,T", 0x47200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
generated by cgit v1.1 at 2024-10-11 07:09:49 +0000