diff options
| -rw-r--r-- | gas/testsuite/gas/mips/allegrex-removed.l | 13 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/allegrex-removed.s | 13 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/mips.exp | 1 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 60 |
4 files changed, 57 insertions, 30 deletions
diff --git a/gas/testsuite/gas/mips/allegrex-removed.l b/gas/testsuite/gas/mips/allegrex-removed.l new file mode 100644 index 0000000..a77d4df --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex-removed.l @@ -0,0 +1,13 @@ +.*: Assembler messages: +.*:2: Error: opcode not supported on this processor: .* \(.*\) `teqi \$11,1024' +.*:3: Error: opcode not supported on this processor: .* \(.*\) `tgei \$11,1024' +.*:4: Error: opcode not supported on this processor: .* \(.*\) `tgeiu \$11,1024' +.*:5: Error: opcode not supported on this processor: .* \(.*\) `tlti \$11,1024' +.*:6: Error: opcode not supported on this processor: .* \(.*\) `tltiu \$11,1024' +.*:7: Error: opcode not supported on this processor: .* \(.*\) `tnei \$11,1024' +.*:8: Error: opcode not supported on this processor: .* \(.*\) `teq \$1,\$2' +.*:9: Error: opcode not supported on this processor: .* \(.*\) `tge \$1,\$2' +.*:10: Error: opcode not supported on this processor: .* \(.*\) `tgeu \$1,\$2' +.*:11: Error: opcode not supported on this processor: .* \(.*\) `tlt \$1,\$2' +.*:12: Error: opcode not supported on this processor: .* \(.*\) `tltu \$1,\$2' +.*:13: Error: opcode not supported on this processor: .* \(.*\) `tne \$1,\$2' diff --git a/gas/testsuite/gas/mips/allegrex-removed.s b/gas/testsuite/gas/mips/allegrex-removed.s new file mode 100644 index 0000000..8dac8a1 --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex-removed.s @@ -0,0 +1,13 @@ + .set noreorder + teqi $11,1024 + tgei $11,1024 + tgeiu $11,1024 + tlti $11,1024 + tltiu $11,1024 + tnei $11,1024 + teq $1,$2 + tge $1,$2 + tgeu $1,$2 + tlt $1,$2 + tltu $1,$2 + tne $1,$2 diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index 2ddbf0c..f657b0e 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -1633,6 +1633,7 @@ if { [istarget mips*-*-vxworks*] } { run_list_test "r5900-error-vu0" "-march=r5900" run_dump_test "allegrex" + run_list_test_arches "allegrex-removed" [mips_arch_list_matching allegrex] run_list_test_arches "ext-ill" [mips_arch_list_matching mips64r2] diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index dca5eda..a31a17d 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -2028,21 +2028,21 @@ const struct mips_opcode mips_builtin_opcodes[] = {"synci", "o(b)", 0x041f0000, 0xfc1f0000, RD_2|SM, 0, I33, 0, 0 }, {"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1, 0, 0 }, {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1, 0, 0 }, -{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* teqi */ -{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tgei */ -{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tgeiu */ -{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2, 0, 0 }, +{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, +{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* teqi */ +{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2, 0, AL }, +{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, +{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* tgei */ +{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2, 0, AL }, +{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, +{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* tgeiu */ +{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2, 0, AL }, {"tlbinv", "", 0x42000003, 0xffffffff, INSN_TLB, 0, I37, TLBINV, 0 }, {"tlbinvf", "", 0x42000004, 0xffffffff, INSN_TLB, 0, I37, TLBINV, 0 }, {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, @@ -2055,21 +2055,21 @@ const struct mips_opcode mips_builtin_opcodes[] = {"tlbginvf", "", 0x4200000c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, {"tlbgwr", "", 0x4200000e, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, {"tlbgp", "", 0x42000010, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, -{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tlti */ -{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tltiu */ -{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tnei */ -{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2, 0, 0 }, +{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, +{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* tlti */ +{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2, 0, AL }, +{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, +{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* tltiu */ +{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2, 0, AL }, +{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, +{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* tnei */ +{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2, 0, AL }, {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, |