diff options
| -rw-r--r-- | gas/testsuite/gas/aarch64/sme-4-illegal.l | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sme2p1-5-bad.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sme2p1-5-bad.l | 103 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sme2p1-5-bad.s | 54 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sme2p1-5.d | 54 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sme2p1-5.s | 54 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 11 | ||||
| -rw-r--r-- | opcodes/aarch64-dis-2.c | 460 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 60 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 18 |
10 files changed, 610 insertions, 210 deletions
diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.l b/gas/testsuite/gas/aarch64/sme-4-illegal.l index a9e9852..db52529 100644 --- a/gas/testsuite/gas/aarch64/sme-4-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-4-illegal.l @@ -1,5 +1,5 @@ [^:]*: Assembler messages: -[^:]*:[0-9]+: Error: expected '{' at operand 1 -- `zero za' +[^:]*:[0-9]+: Error: expected '\[' at operand 1 -- `zero za' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za8\.d}' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za0\.d,za8.d}' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za2\.h}' diff --git a/gas/testsuite/gas/aarch64/sme2p1-5-bad.d b/gas/testsuite/gas/aarch64/sme2p1-5-bad.d new file mode 100644 index 0000000..86a6834 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2p1-5-bad.d @@ -0,0 +1,4 @@ +#name: Negative test of SME2.1 ZERO instructions. +#as: -march=armv9.4-a+sme2p1 +#source: sme2p1-5-bad.s +#error_output: sme2p1-5-bad.l diff --git a/gas/testsuite/gas/aarch64/sme2p1-5-bad.l b/gas/testsuite/gas/aarch64/sme2p1-5-bad.l new file mode 100644 index 0000000..959864a --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2p1-5-bad.l @@ -0,0 +1,103 @@ +.*: Assembler messages: +.*: Error: operand mismatch -- `zero za.s\[w8,0,vgx2\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w8, 0, vgx2\] +.*: Error: operand mismatch -- `zero za.b\[w14,0,vgx2\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w14, 0, vgx2\] +.*: Error: expected a selection register in the range w8-w11 at operand 1 -- `zero za.d\[w2,7,vgx2\]' +.*: Error: immediate offset out of range 0 to 7 at operand 1 -- `zero za.d\[w11,17,vgx2\]' +.*: Error: invalid vector group size at operand 1 -- `zero za.d\[w9,4,vgx3\]' +.*: Error: operand mismatch -- `zero za.h\[w10,3\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w10, 3\] +.*: Error: operand mismatch -- `zero za.s\[w18,0,vgx4\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w18, 0, vgx4\] +.*: Error: operand mismatch -- `zero za.b\[w1,0,vgx4\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w1, 0, vgx4\] +.*: Error: operand mismatch -- `zero za.q\[w8,17,vgx2\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w8, 17, vgx2\] +.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w11,7,vgx3\]' +.*: Error: expected a constant immediate offset at operand 1 -- `zero za.s\[w9,vg\]' +.*: Error: operand mismatch -- `zero za.b\[w10,3\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w10, 3\] +.*: Error: operand mismatch -- `zero za.s\[w18,0:1\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w18, 0:1\] +.*: Error: operand mismatch -- `zero za.s\[w1,0:1\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w1, 0:1\] +.*: Error: operand mismatch -- `zero za.b\[w8,4:5\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w8, 4:5\] +.*: Error: operand mismatch -- `zero za.b\[w11,1:5\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w11, 1:5\] +.*: Error: operand mismatch -- `zero za.h\[w9,2:13\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w9, 2:13\] +.*: Error: the last offset is less than the first offset at operand 1 -- `zero za.h\[w10,16:7\]' +.*: Error: operand mismatch -- `zero za.s\[w18,0:3,vgx2\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w18, 0:3, vgx2\] +.*: Error: operand mismatch -- `zero za.b\[w1,0:1,vgx4\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w1, 0:1, vgx4\] +.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w8,6:7,vg\]' +.*: Error: invalid vector group size at operand 1 -- `zero za.q\[w9,12:13,vgx3\]' +.*: Error: operand mismatch -- `zero za.s\[w18,0:1,vgx4\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w18, 0:1, vgx4\] +.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w1,0:1,vgx3\]' +.*: Error: operand mismatch -- `zero za.b\[w8,16:17,vgx4\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w8, 16:17, vgx4\] +.*: Error: operand mismatch -- `zero za.q\[w9,12:13\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w9, 12:13\] +.*: Error: invalid vector group size at operand 1 -- `zero za.s\[w18,0:3,\]' +.*: Error: operand mismatch -- `zero za.s\[w1,0:3\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w1, 0:3\] +.*: Error: operand mismatch -- `zero za.b\[w8,8:11\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w8, 8:11\] +.*: Error: the last offset is less than the first offset at operand 1 -- `zero za.b\[w11,18:1,vgx3\]' +.*: Error: operand mismatch -- `zero za.h\[w9,4\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w9, 4\] +.*: Error: operand mismatch -- `zero za.h\[w10,10:13\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w10, 10:13\] +.*: Error: operand mismatch -- `zero za.s\[w18,0:3,vgx2\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w18, 0:3, vgx2\] +.*: Error: operand mismatch -- `zero za.s\[w1,0:3,vgx2\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w1, 0:3, vgx2\] +.*: Error: operand mismatch -- `zero za.b\[w8,14:17,vgx2\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w8, 14:17, vgx2\] +.*: Error: invalid vector group size at operand 1 -- `zero za.b\[w11,4:7,vg\]' +.*: Error: operand mismatch -- `zero za.h\[w9,0:3\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w9, 0:3\] +.*: Error: expected a constant immediate offset at operand 1 -- `zero za.q\[w10,vgx2\]' +.*: Error: operand mismatch -- `zero za.s\[w18,0:3,vgx4\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w18, 0:3, vgx4\] +.*: Error: operand mismatch -- `zero za.s\[w1,0:3,vgx4\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w1, 0:3, vgx4\] +.*: Error: operand mismatch -- `zero za.b\[w8,14:17,vgx4\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w8, 14:17, vgx4\] +.*: Error: invalid vector group size at operand 1 -- `zero za.b\[w11,4:7,vg\]' +.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w9,0:3,vgx3\]' +.*: Error: operand mismatch -- `zero za.q\[w10,4\]' +.*: Info: did you mean this\? +.*: Info: zero za.d\[w10, 4\] diff --git a/gas/testsuite/gas/aarch64/sme2p1-5-bad.s b/gas/testsuite/gas/aarch64/sme2p1-5-bad.s new file mode 100644 index 0000000..5b69634 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2p1-5-bad.s @@ -0,0 +1,54 @@ +/* ZERO (single-vector). */ +zero za.s[w8, 0, vgx2] +zero za.b[w14, 0, vgx2] +zero za.d[w2, 7, vgx2] +zero za.d[w11, 17, vgx2] +zero za.d[w9, 4, vgx3] +zero za.h[w10, 3] + +zero za.s[w18, 0, vgx4] +zero za.b[w1, 0, vgx4] +zero za.q[w8, 17, vgx2] +zero za.h[w11, 7, vgx3] +zero za.s[w9, vg] +zero za.b[w10, 3] + +/* ZERO (double-vector). */ +zero za.s[w18, 0:1] +zero za.s[w1, 0:1] +zero za.b[w8, 4:5] +zero za.b[w11, 1:5] +zero za.h[w9, 2:13] +zero za.h[w10, 16:7] + +zero za.s[w18, 0:3, vgx2] +zero za.b[w1, 0:1, vgx4] +zero za.h[w8, 6:7, vg] +zero za.q[w9, 12:13, vgx3] + +zero za.s[w18, 0:1, vgx4] +zero za.h[w1, 0:1, vgx3] +zero za.b[w8, 16:17, vgx4] +zero za.q[w9, 12:13] + +/* ZERO (quad-vector). */ +zero za.s[w18, 0:3,] +zero za.s[w1, 0:3] +zero za.b[w8, 8:11] +zero za.b[w11, 18:1, vgx3] +zero za.h[w9, 4] +zero za.h[w10, 10:13] + +zero za.s[w18, 0:3, vgx2] +zero za.s[w1, 0:3, vgx2] +zero za.b[w8, 14:17, vgx2] +zero za.b[w11, 4:7, vg] +zero za.h[w9, 0:3] +zero za.q[w10, vgx2] + +zero za.s[w18, 0:3, vgx4] +zero za.s[w1, 0:3, vgx4] +zero za.b[w8, 14:17, vgx4] +zero za.b[w11, 4:7, vg] +zero za.h[w9, 0:3, vgx3] +zero za.q[w10, 4] diff --git a/gas/testsuite/gas/aarch64/sme2p1-5.d b/gas/testsuite/gas/aarch64/sme2p1-5.d new file mode 100644 index 0000000..f63a171 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2p1-5.d @@ -0,0 +1,54 @@ +#name: Test of SME2.1 ZERO instructions. +#as: -march=armv9.4-a+sme2p1 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: c00c0000 zero za.d\[w8, 0, vgx2\] +.*: c00c6000 zero za.d\[w11, 0, vgx2\] +.*: c00c0007 zero za.d\[w8, 7, vgx2\] +.*: c00c6007 zero za.d\[w11, 7, vgx2\] +.*: c00c2004 zero za.d\[w9, 4, vgx2\] +.*: c00c4003 zero za.d\[w10, 3, vgx2\] +.*: c00e0000 zero za.d\[w8, 0, vgx4\] +.*: c00e6000 zero za.d\[w11, 0, vgx4\] +.*: c00e0007 zero za.d\[w8, 7, vgx4\] +.*: c00e6007 zero za.d\[w11, 7, vgx4\] +.*: c00e2004 zero za.d\[w9, 4, vgx4\] +.*: c00e4003 zero za.d\[w10, 3, vgx4\] +.*: c00c8000 zero za.d\[w8, 0:1\] +.*: c00ce000 zero za.d\[w11, 0:1\] +.*: c00c8007 zero za.d\[w8, 14:15\] +.*: c00ce007 zero za.d\[w11, 14:15\] +.*: c00ca001 zero za.d\[w9, 2:3\] +.*: c00cc003 zero za.d\[w10, 6:7\] +.*: c00d0000 zero za.d\[w8, 0:1, vgx2\] +.*: c00d6000 zero za.d\[w11, 0:1, vgx2\] +.*: c00d0003 zero za.d\[w8, 6:7, vgx2\] +.*: c00d2001 zero za.d\[w9, 2:3, vgx2\] +.*: c00d8000 zero za.d\[w8, 0:1, vgx4\] +.*: c00de000 zero za.d\[w11, 0:1, vgx4\] +.*: c00d8003 zero za.d\[w8, 6:7, vgx4\] +.*: c00da001 zero za.d\[w9, 2:3, vgx4\] +.*: c00e8000 zero za.d\[w8, 0:3\] +.*: c00ee000 zero za.d\[w11, 0:3\] +.*: c00e8002 zero za.d\[w8, 8:11\] +.*: c00ee002 zero za.d\[w11, 8:11\] +.*: c00ea001 zero za.d\[w9, 4:7\] +.*: c00ec000 zero za.d\[w10, 0:3\] +.*: c00f0000 zero za.d\[w8, 0:3, vgx2\] +.*: c00f6000 zero za.d\[w11, 0:3, vgx2\] +.*: c00f0001 zero za.d\[w8, 4:7, vgx2\] +.*: c00f6001 zero za.d\[w11, 4:7, vgx2\] +.*: c00f2000 zero za.d\[w9, 0:3, vgx2\] +.*: c00f4001 zero za.d\[w10, 4:7, vgx2\] +.*: c00f8000 zero za.d\[w8, 0:3, vgx4\] +.*: c00fe000 zero za.d\[w11, 0:3, vgx4\] +.*: c00f8001 zero za.d\[w8, 4:7, vgx4\] +.*: c00fe001 zero za.d\[w11, 4:7, vgx4\] +.*: c00fa000 zero za.d\[w9, 0:3, vgx4\] +.*: c00fc001 zero za.d\[w10, 4:7, vgx4\] diff --git a/gas/testsuite/gas/aarch64/sme2p1-5.s b/gas/testsuite/gas/aarch64/sme2p1-5.s new file mode 100644 index 0000000..bd25682 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2p1-5.s @@ -0,0 +1,54 @@ +/* ZERO (single-vector). */ +zero za.d[w8, 0, vgx2] +zero za.d[w11, 0, vgx2] +zero za.d[w8, 7, vgx2] +zero za.d[w11, 7, vgx2] +zero za.d[w9, 4, vgx2] +zero za.d[w10, 3, vgx2] + +zero za.d[w8, 0, vgx4] +zero za.d[w11, 0, vgx4] +zero za.d[w8, 7, vgx4] +zero za.d[w11, 7, vgx4] +zero za.d[w9, 4, vgx4] +zero za.d[w10, 3, vgx4] + +/* ZERO (double-vector). */ +zero za.d[w8, 0:1] +zero za.d[w11, 0:1] +zero za.d[w8, 14:15] +zero za.d[w11, 14:15] +zero za.d[w9, 2:3] +zero za.d[w10, 6:7] + +zero za.d[w8, 0:1, vgx2] +zero za.d[w11, 0:1, vgx2] +zero za.d[w8, 6:7, vgx2] +zero za.d[w9, 2:3, vgx2] + +zero za.d[w8, 0:1, vgx4] +zero za.d[w11, 0:1, vgx4] +zero za.d[w8, 6:7, vgx4] +zero za.d[w9, 2:3, vgx4] + +/* ZERO (quad-vector). */ +zero za.d[w8, 0:3] +zero za.d[w11, 0:3] +zero za.d[w8, 8:11] +zero za.d[w11, 8:11] +zero za.d[w9, 4:7] +zero za.d[w10, 0:3] + +zero za.d[w8, 0:3, vgx2] +zero za.d[w11, 0:3, vgx2] +zero za.d[w8, 4:7, vgx2] +zero za.d[w11, 4:7, vgx2] +zero za.d[w9, 0:3, vgx2] +zero za.d[w10, 4:7, vgx2] + +zero za.d[w8, 0:3, vgx4] +zero za.d[w11, 0:3, vgx4] +zero za.d[w8, 4:7, vgx4] +zero za.d[w11, 4:7, vgx4] +zero za.d[w9, 0:3, vgx4] +zero za.d[w10, 4:7, vgx4] diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 5a2b99d..1b01931 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1387,7 +1387,10 @@ extern const aarch64_opcode aarch64_opcode_table[]; #define F_OPD_SIZE (1ULL << 34) /* RCPC3 instruction has the field of 'size'. */ #define F_RCPC3_SIZE (1ULL << 35) -/* Next bit is 36. */ +/* This instruction need VGx2 or VGx4 mandatorily in the operand passed to + assembler. */ +#define F_VG_REQ (1ULL << 36) +/* Next bit is 37. */ /* Instruction constraints. */ /* This instruction has a predication constraint on the instruction at PC+4. */ @@ -1451,6 +1454,12 @@ get_opcode_dependent_value (const aarch64_opcode *opcode) } static inline bool +get_opcode_dependent_vg_status (const aarch64_opcode *opcode) +{ + return (opcode->flags >> 36) & 0x1; +} + +static inline bool opcode_has_special_coder (const aarch64_opcode *opcode) { return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 7a7af4a..4138ec8 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -271,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x000101x00xxxxxxxxxxxxxx luti4. */ - return 3420; + return 3428; } else { @@ -310,7 +310,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx01101x00xxxxxxxxxxxxxx luti4. */ - return 3421; + return 3429; } else { @@ -408,21 +408,109 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 22) & 0x1) == 0) { - if (((word >> 14) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000x00011xxx0xx00xxxxxxxxxx - luti2. */ - return 2668; + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 16) & 0x1) == 0) + { + if (((word >> 17) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000000011000xxx00xxxxxxxxxx + zero. */ + return 3317; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000000011100xxx00xxxxxxxxxx + zero. */ + return 3318; + } + } + else + { + if (((word >> 17) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000000011010xxx00xxxxxxxxxx + zero. */ + return 3320; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000000011110xxx00xxxxxxxxxx + zero. */ + return 3323; + } + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + if (((word >> 17) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000000011001xxx00xxxxxxxxxx + zero. */ + return 3319; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000000011101xxx00xxxxxxxxxx + zero. */ + return 3322; + } + } + else + { + if (((word >> 17) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000000011011xxx00xxxxxxxxxx + zero. */ + return 3321; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000000011111xxx00xxxxxxxxxx + zero. */ + return 3324; + } + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000x00011xxx1xx00xxxxxxxxxx - luti2. */ - return 2667; + if (((word >> 14) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000100011xxx0xx00xxxxxxxxxx + luti2. */ + return 2668; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000100011xxx1xx00xxxxxxxxxx + luti2. */ + return 2667; + } } } else @@ -454,7 +542,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010011x1xxxx00xxxxxxxxxx movt. */ - return 3422; + return 3430; } } else @@ -1278,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000000101xxxxxxxxxxxxxxxx00xxx fmopa. */ - return 3488; + return 3496; } else { @@ -1286,7 +1374,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000000101xxxxxxxxxxxxxxxx01xxx fmopa. */ - return 3487; + return 3495; } } else @@ -1634,7 +1722,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx1xx0xxxxx1000xxx fmlall. */ - return 3481; + return 3489; } } } @@ -1664,7 +1752,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxxxxx1xxxxxx00xxxx fdot. */ - return 3466; + return 3474; } } else @@ -2036,7 +2124,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxxxxx0xxxxxx100xxx fmlall. */ - return 3480; + return 3488; } } } @@ -2141,7 +2229,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxxxxx1xxxxxx10xxxx fmlal. */ - return 3473; + return 3481; } } } @@ -2314,7 +2402,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxxxxx1xxxxxx11xxxx fmlal. */ - return 3472; + return 3480; } } } @@ -2356,7 +2444,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010100xxxxxxxxxxxxxxxx0xxx fmlall. */ - return 3479; + return 3487; } else { @@ -2724,7 +2812,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xx0xxxxxx111xxx fdot. */ - return 3459; + return 3467; } else { @@ -2793,7 +2881,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx0xxxxxx001xxx fdot. */ - return 3460; + return 3468; } else { @@ -2872,7 +2960,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011100xxxxxxx0xxxxxxx0xxxx fmlal. */ - return 3471; + return 3479; } else { @@ -2927,7 +3015,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxx0xx01xxxxx00xxxx fvdotb. */ - return 3490; + return 3498; } else { @@ -2945,7 +3033,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxxxxx0xxxxxx10xxxx fdot. */ - return 3465; + return 3473; } } } @@ -3019,7 +3107,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxxxxx1xxxxxx10xxxx fvdot. */ - return 3489; + return 3497; } } } @@ -3099,7 +3187,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx0xx01xxxxxx1xxxx fvdott. */ - return 3491; + return 3499; } else { @@ -3276,7 +3364,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx000xxxx10000x fmlall. */ - return 3485; + return 3493; } else { @@ -3284,7 +3372,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx000xxxx10000x fmlall. */ - return 3486; + return 3494; } } } @@ -3339,7 +3427,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx000xxxxx00x1x fmlall. */ - return 3483; + return 3491; } else { @@ -3347,7 +3435,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx000xxxxx00x1x fmlall. */ - return 3484; + return 3492; } } } @@ -3401,7 +3489,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx100xxxx100xxx fdot. */ - return 3469; + return 3477; } else { @@ -3409,7 +3497,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx100xxxx100xxx fdot. */ - return 3470; + return 3478; } } } @@ -3471,7 +3559,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxxx00xx010xxxx1000xx fmlal. */ - return 3477; + return 3485; } else { @@ -3479,7 +3567,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxxx10xx010xxxx1000xx fmlal. */ - return 3478; + return 3486; } } } @@ -3534,7 +3622,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx010xxxxx001xx fmlal. */ - return 3475; + return 3483; } else { @@ -3542,7 +3630,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx010xxxxx001xx fmlal. */ - return 3476; + return 3484; } } } @@ -3611,7 +3699,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx001xxxxx000xx fmlall. */ - return 3482; + return 3490; } } else @@ -3694,7 +3782,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx011xxxxx00xxx fmlal. */ - return 3474; + return 3482; } } else @@ -3715,7 +3803,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx1x00xx111xxxxx00xxx fadd. */ - return 3423; + return 3431; } } else @@ -3734,7 +3822,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx1x10xx111xxxxx00xxx fadd. */ - return 3424; + return 3432; } } } @@ -3860,7 +3948,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx100xxxx110xxx fdot. */ - return 3463; + return 3471; } else { @@ -3868,7 +3956,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx100xxxx110xxx fdot. */ - return 3464; + return 3472; } } } @@ -4159,7 +4247,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx100xxxxx01xxx fdot. */ - return 3467; + return 3475; } else { @@ -4167,7 +4255,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx100xxxxx01xxx fdot. */ - return 3468; + return 3476; } } } @@ -4438,7 +4526,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx1x00xx111xxxxx01xxx fsub. */ - return 3425; + return 3433; } } else @@ -4457,7 +4545,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx1x10xx111xxxxx01xxx fsub. */ - return 3426; + return 3434; } } } @@ -4519,7 +4607,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx100xxxxx11xxx fdot. */ - return 3461; + return 3469; } else { @@ -4527,7 +4615,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx100xxxxx11xxx fdot. */ - return 3462; + return 3470; } } } @@ -5062,7 +5150,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx101000xx1x0xxxx0 fscale. */ - return 3397; + return 3405; } } else @@ -5210,7 +5298,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x0100100111000xxxx0xxxxx fcvt. */ - return 3394; + return 3402; } else { @@ -5218,7 +5306,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x1100100111000xxxx0xxxxx bfcvt. */ - return 3389; + return 3397; } } else @@ -5227,7 +5315,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx110100111000xxxx0xxxxx fcvt. */ - return 3395; + return 3403; } } else @@ -5278,7 +5366,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx100111000xxxx1xxxxx fcvtn. */ - return 3396; + return 3404; } } } @@ -5361,7 +5449,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010010x110111000xxxxxxxxx0 f1cvt. */ - return 3390; + return 3398; } else { @@ -5369,7 +5457,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011010x110111000xxxxxxxxx0 f2cvt. */ - return 3391; + return 3399; } } else @@ -5380,7 +5468,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010110x110111000xxxxxxxxx0 bf1cvt. */ - return 3385; + return 3393; } else { @@ -5388,7 +5476,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011110x110111000xxxxxxxxx0 bf2cvt. */ - return 3386; + return 3394; } } } @@ -5423,7 +5511,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001001xxx10111000xxxxxxxxx1 f1cvtl. */ - return 3392; + return 3400; } else { @@ -5431,7 +5519,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxx10111000xxxxxxxxx1 f2cvtl. */ - return 3393; + return 3401; } } else @@ -5442,7 +5530,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001011xxx10111000xxxxxxxxx1 bf1cvtl. */ - return 3387; + return 3395; } else { @@ -5450,7 +5538,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxx10111000xxxxxxxxx1 bf2cvtl. */ - return 3388; + return 3396; } } } @@ -5719,7 +5807,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1100xx100xxxx0 fscale. */ - return 3399; + return 3407; } } else @@ -5895,7 +5983,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1010xx100xxxx0 fscale. */ - return 3398; + return 3406; } else { @@ -5903,7 +5991,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1110xx100xxxx0 fscale. */ - return 3400; + return 3408; } } } @@ -11071,7 +11159,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x11010000xxxxxxx1xxxxxxxxxxxxx addpt. */ - return 3401; + return 3409; } else { @@ -11079,7 +11167,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x11010000xxxxxxx1xxxxxxxxxxxxx subpt. */ - return 3402; + return 3410; } } } @@ -11997,7 +12085,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxxx1011x11xxxxx0xxxxxxxxxxxxxxx maddpt. */ - return 3403; + return 3411; } else { @@ -12005,7 +12093,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxxx1011x11xxxxx1xxxxxxxxxxxxxxx msubpt. */ - return 3404; + return 3412; } } } @@ -12090,7 +12178,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx000100000xxxxxxxxxxxxx addpt. */ - return 3405; + return 3413; } else { @@ -12197,7 +12285,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx000101000xxxxxxxxxxxxx subpt. */ - return 3407; + return 3415; } else { @@ -12402,7 +12490,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx1xxxxx000010xxxxxxxxxx addpt. */ - return 3406; + return 3414; } else { @@ -12443,7 +12531,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx1xxxxx000011xxxxxxxxxx subpt. */ - return 3408; + return 3416; } else { @@ -14101,7 +14189,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx110100xxxxxxxxxx mlapt. */ - return 3410; + return 3418; } } else @@ -14131,7 +14219,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx110110xxxxxxxxxx madpt. */ - return 3409; + return 3417; } } } @@ -14439,7 +14527,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx00x100001xxxxxxxxxxxxx smaxqv. */ - return 3319; + return 3327; } else { @@ -14447,7 +14535,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx01x100001xxxxxxxxxxxxx orqv. */ - return 3330; + return 3338; } } else @@ -14458,7 +14546,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx0x0101001xxxxxxxxxxxxx addqv. */ - return 3317; + return 3325; } else { @@ -14468,7 +14556,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx001101001xxxxxxxxxxxxx umaxqv. */ - return 3321; + return 3329; } else { @@ -14476,7 +14564,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx011101001xxxxxxxxxxxxx eorqv. */ - return 3323; + return 3331; } } } @@ -14513,7 +14601,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx00x110001xxxxxxxxxxxxx sminqv. */ - return 3320; + return 3328; } else { @@ -14521,7 +14609,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx01x110001xxxxxxxxxxxxx andqv. */ - return 3318; + return 3326; } } } @@ -14541,7 +14629,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx0xx111001xxxxxxxxxxxxx uminqv. */ - return 3322; + return 3330; } } } @@ -15285,7 +15373,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 110001x0x00xxxxx101xxxxxxxxxxxxx ld1q. */ - return 3346; + return 3354; } else { @@ -16299,7 +16387,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111x00xxxxxxxxxx zipq1. */ - return 3336; + return 3344; } else { @@ -16309,7 +16397,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111010xxxxxxxxxx uzpq1. */ - return 3334; + return 3342; } else { @@ -16317,7 +16405,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111110xxxxxxxxxx tblq. */ - return 3331; + return 3339; } } } @@ -16329,7 +16417,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111x01xxxxxxxxxx zipq2. */ - return 3337; + return 3345; } else { @@ -16337,7 +16425,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111x11xxxxxxxxxx uzpq2. */ - return 3335; + return 3343; } } } @@ -16817,7 +16905,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0x00xxxxx000xxxxxxxxxxxxx st3q. */ - return 3355; + return 3363; } else { @@ -16827,7 +16915,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0010xxxxx000xxxxxxxxxxxxx st2q. */ - return 3354; + return 3362; } else { @@ -16835,7 +16923,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0110xxxxx000xxxxxxxxxxxxx st4q. */ - return 3356; + return 3364; } } } @@ -17282,7 +17370,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0x0000101xxxxxxxxxxxxx faddqv. */ - return 3324; + return 3332; } else { @@ -17299,7 +17387,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0xx100101xxxxxxxxxxxxx fmaxnmqv. */ - return 3325; + return 3333; } } else @@ -17340,7 +17428,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0xx110101xxxxxxxxxxxxx fmaxqv. */ - return 3326; + return 3334; } } } @@ -17362,7 +17450,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0xx101101xxxxxxxxxxxxx fminnmqv. */ - return 3327; + return 3335; } } else @@ -17381,7 +17469,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0xx111101xxxxxxxxxxxxx fminqv. */ - return 3328; + return 3336; } } } @@ -17501,7 +17589,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x0xx01xxxx111xxxxxxxxxxxxx ld2q. */ - return 3347; + return 3355; } } } @@ -17637,7 +17725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x0xx1xxxxx100xxxxxxxxxxxxx ld2q. */ - return 3350; + return 3358; } } else @@ -17782,7 +17870,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x00x1xxxxx000xxxxxxxxxxxxx st2q. */ - return 3357; + return 3365; } } else @@ -17825,7 +17913,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0101xxxxx000xxxxxxxxxxxxx st3q. */ - return 3358; + return 3366; } } else @@ -17866,7 +17954,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0111xxxxx000xxxxxxxxxxxxx st4q. */ - return 3359; + return 3367; } } } @@ -17895,7 +17983,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0001xxxxx0100x1xxxxxxxxxx fdot. */ - return 3446; + return 3454; } } else @@ -17904,7 +17992,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0001xxxxx0101xxxxxxxxxxxx fmlalb. */ - return 3448; + return 3456; } } else @@ -17945,7 +18033,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx0101xxxxxxxxxxxx fmlalt. */ - return 3458; + return 3466; } } else @@ -17978,7 +18066,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xx1xxxxxxxxxx fdot. */ - return 3444; + return 3452; } } else @@ -18049,7 +18137,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx100010xxxxxxxxxx fmlallbb. */ - return 3449; + return 3457; } } else @@ -18058,7 +18146,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1000x1xxxxxxxxxx fdot. */ - return 3445; + return 3453; } } else @@ -18067,7 +18155,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1100xxxxxxxxxxxx fmlallbb. */ - return 3450; + return 3458; } } else @@ -18076,7 +18164,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1x01xxxxxxxxxxxx fmlallbt. */ - return 3451; + return 3459; } } else @@ -18103,7 +18191,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx100010xxxxxxxxxx fmlalb. */ - return 3447; + return 3455; } } else @@ -18121,7 +18209,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx1100xxxxxxxxxxxx fmlalltb. */ - return 3454; + return 3462; } } else @@ -18130,7 +18218,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx1x01xxxxxxxxxxxx fmlalt. */ - return 3457; + return 3465; } } else @@ -18163,7 +18251,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx100xx1xxxxxxxxxx fdot. */ - return 3443; + return 3451; } } else @@ -18172,7 +18260,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx110xxxxxxxxxxxxx fmlallbt. */ - return 3452; + return 3460; } } else @@ -18204,7 +18292,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx110xxxxxxxxxxxxx fmlalltt. */ - return 3456; + return 3464; } } else @@ -18503,7 +18591,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0xx1xxxxx001xxxxxxxxxxxxx st1q. */ - return 3353; + return 3361; } } else @@ -18518,7 +18606,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1010xxxxxxxxxxxx fmlalltb. */ - return 3453; + return 3461; } else { @@ -18526,7 +18614,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1011xxxxxxxxxxxx fmlalltt. */ - return 3455; + return 3463; } } else @@ -19244,7 +19332,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1001010x0001110xxxxxxxxxx pmov. */ - return 3338; + return 3346; } else { @@ -19252,7 +19340,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1001011x0001110xxxxxxxxxx pmov. */ - return 3339; + return 3347; } } else @@ -19261,7 +19349,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x101101xx0001110xxxxxxxxxx pmov. */ - return 3340; + return 3348; } } else @@ -19270,7 +19358,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x11x101xx0001110xxxxxxxxxx pmov. */ - return 3341; + return 3349; } } else @@ -19316,7 +19404,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1001x10x1001110xxxxxxxxxx pmov. */ - return 3342; + return 3350; } else { @@ -19324,7 +19412,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1001x11x1001110xxxxxxxxxx pmov. */ - return 3343; + return 3351; } } else @@ -19333,7 +19421,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1011x1xx1001110xxxxxxxxxx pmov. */ - return 3344; + return 3352; } } else @@ -19342,7 +19430,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x11x1x1xx1001110xxxxxxxxxx pmov. */ - return 3345; + return 3353; } } } @@ -19361,7 +19449,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1x01xxxxx001001xxxxxxxxxx dupq. */ - return 3329; + return 3337; } else { @@ -19369,7 +19457,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1x11xxxxx001001xxxxxxxxxx extq. */ - return 3333; + return 3341; } } else @@ -19378,7 +19466,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1xx1xxxxx001101xxxxxxxxxx tbxq. */ - return 3332; + return 3340; } } else @@ -20981,7 +21069,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101100xxxxxxxxxx luti2. */ - return 3415; + return 3423; } } else @@ -20990,7 +21078,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101x10xxxxxxxxxx luti2. */ - return 3416; + return 3424; } } else @@ -21003,7 +21091,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101001xxxxxxxxxx luti4. */ - return 3417; + return 3425; } else { @@ -21011,7 +21099,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101101xxxxxxxxxx luti4. */ - return 3418; + return 3426; } } else @@ -21020,7 +21108,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101x11xxxxxxxxxx luti4. */ - return 3419; + return 3427; } } } @@ -21971,7 +22059,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x00xxxxxxxxxx f1cvt. */ - return 3377; + return 3385; } else { @@ -21979,7 +22067,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x10xxxxxxxxxx bf1cvt. */ - return 3373; + return 3381; } } else @@ -21990,7 +22078,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x01xxxxxxxxxx f2cvt. */ - return 3378; + return 3386; } else { @@ -21998,7 +22086,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x11xxxxxxxxxx bf2cvt. */ - return 3374; + return 3382; } } } @@ -22043,7 +22131,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x00xxxxxxxxxx fcvtn. */ - return 3382; + return 3390; } else { @@ -22051,7 +22139,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x10xxxxxxxxxx bfcvtn. */ - return 3381; + return 3389; } } else @@ -22062,7 +22150,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x01xxxxxxxxxx fcvtnb. */ - return 3383; + return 3391; } else { @@ -22070,7 +22158,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x11xxxxxxxxxx fcvtnt. */ - return 3384; + return 3392; } } } @@ -22131,7 +22219,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x00xxxxxxxxxx f1cvtlt. */ - return 3379; + return 3387; } else { @@ -22139,7 +22227,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x10xxxxxxxxxx bf1cvtlt. */ - return 3375; + return 3383; } } else @@ -22150,7 +22238,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x01xxxxxxxxxx f2cvtlt. */ - return 3380; + return 3388; } else { @@ -22158,7 +22246,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x11xxxxxxxxxx bf2cvtlt. */ - return 3376; + return 3384; } } } @@ -23484,7 +23572,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x01xxxx111xxxxxxxxxxxxx ld3q. */ - return 3348; + return 3356; } else { @@ -23492,7 +23580,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x01xxxx111xxxxxxxxxxxxx ld4q. */ - return 3349; + return 3357; } } } @@ -24665,7 +24753,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx100xxxxxxxxxxxxx ld3q. */ - return 3351; + return 3359; } else { @@ -24673,7 +24761,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx100xxxxxxxxxxxxx ld4q. */ - return 3352; + return 3360; } } else @@ -26738,7 +26826,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110100xxxxxxxx100xxxxxxxxxx luti2. */ - return 3411; + return 3419; } } } @@ -26752,7 +26840,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110010xxxxxxxx000xxxxxxxxxx luti4. */ - return 3413; + return 3421; } else { @@ -26760,7 +26848,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110010xxxxxxxx100xxxxxxxxxx luti4. */ - return 3414; + return 3422; } } else @@ -26769,7 +26857,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110110xxxxxxxxx00xxxxxxxxxx luti2. */ - return 3412; + return 3420; } } } @@ -26885,7 +26973,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110x00xxxxxx10001xxxxxxxxxx fmlallbb. */ - return 3435; + return 3443; } else { @@ -26893,7 +26981,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110x00xxxxxx10001xxxxxxxxxx fmlalltb. */ - return 3437; + return 3445; } } else @@ -26904,7 +26992,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110x10xxxxxx10001xxxxxxxxxx fmlallbt. */ - return 3436; + return 3444; } else { @@ -26912,7 +27000,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110x10xxxxxx10001xxxxxxxxxx fmlalltt. */ - return 3438; + return 3446; } } } @@ -27000,7 +27088,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110x00xxxxxx11101xxxxxxxxxx fcvtn. */ - return 3368; + return 3376; } else { @@ -27008,7 +27096,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110x00xxxxxx11101xxxxxxxxxx fcvtn2. */ - return 3369; + return 3377; } } else @@ -27017,7 +27105,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110x10xxxxxx11101xxxxxxxxxx fcvtn. */ - return 3370; + return 3378; } } } @@ -27160,7 +27248,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110x00xxxxxx11111xxxxxxxxxx fdot. */ - return 3427; + return 3435; } else { @@ -27170,7 +27258,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110010xxxxxx11111xxxxxxxxxx fdot. */ - return 3429; + return 3437; } else { @@ -27180,7 +27268,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110110xxxxxx11111xxxxxxxxxx fmlalb. */ - return 3431; + return 3439; } else { @@ -27188,7 +27276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110110xxxxxx11111xxxxxxxxxx fmlalt. */ - return 3432; + return 3440; } } } @@ -27462,7 +27550,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110110xxxxx0x1111xxxxxxxxxx fscale. */ - return 3371; + return 3379; } } } @@ -28854,7 +28942,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110001xxxx1011110xxxxxxxxxx f1cvtl. */ - return 3364; + return 3372; } else { @@ -28862,7 +28950,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110001xxxx1011110xxxxxxxxxx f1cvtl2. */ - return 3365; + return 3373; } } else @@ -28873,7 +28961,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110101xxxx1011110xxxxxxxxxx bf1cvtl. */ - return 3360; + return 3368; } else { @@ -28881,7 +28969,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110101xxxx1011110xxxxxxxxxx bf1cvtl2. */ - return 3361; + return 3369; } } } @@ -28895,7 +28983,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110011xxxx1011110xxxxxxxxxx f2cvtl. */ - return 3366; + return 3374; } else { @@ -28903,7 +28991,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110011xxxx1011110xxxxxxxxxx f2cvtl2. */ - return 3367; + return 3375; } } else @@ -28914,7 +29002,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110111xxxx1011110xxxxxxxxxx bf2cvtl. */ - return 3362; + return 3370; } else { @@ -28922,7 +29010,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110111xxxx1011110xxxxxxxxxx bf2cvtl2. */ - return 3363; + return 3371; } } } @@ -30921,7 +31009,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011101x1xxxxx111111xxxxxxxxxx fscale. */ - return 3372; + return 3380; } } } @@ -32637,7 +32725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx0000x0xxxxxxxxxx fdot. */ - return 3428; + return 3436; } else { @@ -32667,7 +32755,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx0000x0xxxxxxxxxx fdot. */ - return 3430; + return 3438; } else { @@ -32677,7 +32765,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx0000x0xxxxxxxxxx fmlalb. */ - return 3433; + return 3441; } else { @@ -32685,7 +32773,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx0000x0xxxxxxxxxx fmlalt. */ - return 3434; + return 3442; } } } @@ -33227,7 +33315,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x010111100xxxxxx1000x0xxxxxxxxxx fmlallbb. */ - return 3439; + return 3447; } else { @@ -33235,7 +33323,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x110111100xxxxxx1000x0xxxxxxxxxx fmlalltb. */ - return 3441; + return 3449; } } else @@ -33266,7 +33354,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111x1xxxxxx1000x0xxxxxxxxxx fmlallbt. */ - return 3440; + return 3448; } else { @@ -33274,7 +33362,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111x1xxxxxx1000x0xxxxxxxxxx fmlalltt. */ - return 3442; + return 3450; } } } diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index f65f83a..b71d354 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1629,13 +1629,14 @@ check_reglist (const aarch64_opnd_info *opnd, - an initial immediate offset that is a multiple of RANGE_SIZE in the range [0, MAX_VALUE * RANGE_SIZE] - - a vector group size of GROUP_SIZE. */ + - a vector group size of GROUP_SIZE. + - STATUS_VG for cases where VGx2 or VGx4 is mandatory. */ static bool check_za_access (const aarch64_opnd_info *opnd, aarch64_operand_error *mismatch_detail, int idx, int min_wreg, int max_value, unsigned int range_size, - int group_size) + int group_size, bool status_vg) { if (!value_in_range_p (opnd->indexed_za.index.regno, min_wreg, min_wreg + 3)) { @@ -1687,8 +1688,8 @@ check_za_access (const aarch64_opnd_info *opnd, } /* The vector group specifier is optional in assembly code. */ - if (opnd->indexed_za.group_size != 0 - && opnd->indexed_za.group_size != group_size) + if (opnd->indexed_za.group_size != group_size + && (status_vg || opnd->indexed_za.group_size != 0 )) { set_invalid_vg_size (mismatch_detail, idx, group_size); return false; @@ -1923,7 +1924,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, size = aarch64_get_qualifier_esize (opnd->qualifier); max_value = 16 / size - 1; if (!check_za_access (opnd, mismatch_detail, idx, - 12, max_value, 1, 0)) + 12, max_value, 1, 0, get_opcode_dependent_value (opcode))) return 0; break; @@ -1993,93 +1994,108 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, size = aarch64_get_qualifier_esize (opnd->qualifier); max_value = 16 / size - 1; if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, 1, - get_opcode_dependent_value (opcode))) + get_opcode_dependent_value (opcode), + get_opcode_dependent_vg_status (opcode))) return 0; break; case AARCH64_OPND_SME_ZA_array_off4: if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, 1, - get_opcode_dependent_value (opcode))) + get_opcode_dependent_value (opcode), + get_opcode_dependent_vg_status (opcode))) return 0; break; case AARCH64_OPND_SME_ZA_array_off3_0: case AARCH64_OPND_SME_ZA_array_off3_5: if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 1, - get_opcode_dependent_value (opcode))) + get_opcode_dependent_value (opcode), + get_opcode_dependent_vg_status (opcode))) return 0; break; case AARCH64_OPND_SME_ZA_array_off1x4: if (!check_za_access (opnd, mismatch_detail, idx, 8, 1, 4, - get_opcode_dependent_value (opcode))) + get_opcode_dependent_value (opcode), + get_opcode_dependent_vg_status (opcode))) return 0; break; case AARCH64_OPND_SME_ZA_array_off2x2: if (!check_za_access (opnd, mismatch_detail, idx, 8, 3, 2, - get_opcode_dependent_value (opcode))) + get_opcode_dependent_value (opcode), + get_opcode_dependent_vg_status (opcode))) return 0; break; case AARCH64_OPND_SME_ZA_array_off2x4: if (!check_za_access (opnd, mismatch_detail, idx, 8, 3, 4, - get_opcode_dependent_value (opcode))) + get_opcode_dependent_value (opcode), + get_opcode_dependent_vg_status (opcode))) return 0; break; case AARCH64_OPND_SME_ZA_array_off3x2: if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 2, - get_opcode_dependent_value (opcode))) + get_opcode_dependent_value (opcode), + get_opcode_dependent_vg_status (opcode))) return 0; break; case AARCH64_OPND_SME_ZA_array_vrsb_1: if (!check_za_access (opnd, mismatch_detail, idx, 12, 7, 2, - get_opcode_dependent_value (opcode))) + get_opcode_dependent_value (opcode), + get_opcode_dependent_vg_status (opcode))) return 0; break; case AARCH64_OPND_SME_ZA_array_vrsh_1: if (!check_za_access (opnd, mismatch_detail, idx, 12, 3, 2, - get_opcode_dependent_value (opcode))) + get_opcode_dependent_value (opcode), + get_opcode_dependent_vg_status (opcode))) return 0; break; case AARCH64_OPND_SME_ZA_array_vrss_1: if (!check_za_access (opnd, mismatch_detail, idx, 12, 1, 2, - get_opcode_dependent_value (opcode))) + get_opcode_dependent_value (opcode), + get_opcode_dependent_vg_status (opcode))) return 0; break; case AARCH64_OPND_SME_ZA_array_vrsd_1: if (!check_za_access (opnd, mismatch_detail, idx, 12, 0, 2, - get_opcode_dependent_value (opcode))) + get_opcode_dependent_value (opcode), + get_opcode_dependent_vg_status (opcode))) return 0; break; case AARCH64_OPND_SME_ZA_array_vrsb_2: if (!check_za_access (opnd, mismatch_detail, idx, 12, 3, 4, - get_opcode_dependent_value (opcode))) + get_opcode_dependent_value (opcode), + get_opcode_dependent_vg_status (opcode))) return 0; break; case AARCH64_OPND_SME_ZA_array_vrsh_2: if (!check_za_access (opnd, mismatch_detail, idx, 12, 1, 4, - get_opcode_dependent_value (opcode))) + get_opcode_dependent_value (opcode), + get_opcode_dependent_vg_status (opcode))) return 0; break; case AARCH64_OPND_SME_ZA_ARRAY4: if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, 1, - get_opcode_dependent_value (opcode))) + get_opcode_dependent_value (opcode), + get_opcode_dependent_vg_status (opcode))) return 0; break; case AARCH64_OPND_SME_ZA_array_vrss_2: case AARCH64_OPND_SME_ZA_array_vrsd_2: if (!check_za_access (opnd, mismatch_detail, idx, 12, 0, 4, - get_opcode_dependent_value (opcode))) + get_opcode_dependent_value (opcode), + get_opcode_dependent_vg_status (opcode))) return 0; break; @@ -2090,8 +2106,8 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, max_value = 16 / num / size; if (max_value > 0) max_value -= 1; - if (!check_za_access (opnd, mismatch_detail, idx, - 12, max_value, num, 0)) + if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, num, + 0, get_opcode_dependent_value (opcode))) return 0; break; diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 38be471..d49ad36 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1606,6 +1606,10 @@ { \ QLF3(S_B,P_Z,NIL), \ } +#define OP_SVE_D \ +{ \ + QLF1(S_D), \ +} #define OP_SVE_DD \ { \ QLF2(S_D,S_D), \ @@ -6668,6 +6672,20 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2p1_INSN ("movaz", 0xc0c20200, 0xffff1e00, sme2_movaz, 0, OP2 (SVE_Zd, SME_ZA_ARRAY4), OP_SVE_DD, 0, 0), SME2p1_INSN ("movaz", 0xc0c30200, 0xffff1e00, sme2_movaz, 0, OP2 (SVE_Zd, SME_ZA_ARRAY4), OP_SVE_QQ, 0, 0), + /* ZERO (single-vector). */ + SME2p1_INSN ("zero", 0xc00c0000, 0xffff9ff8, sme2_movaz, 0, OP1 (SME_ZA_array_off3_0), OP_SVE_D, F_OD (2) | F_VG_REQ, 0), + SME2p1_INSN ("zero", 0xc00e0000, 0xffff9ff8, sme2_movaz, 0, OP1 (SME_ZA_array_off3_0), OP_SVE_D, F_OD (4) | F_VG_REQ, 0), + + /* ZERO (double-vector). */ + SME2p1_INSN ("zero", 0xc00c8000, 0xffff9ff8, sme2_movaz, 0, OP1 (SME_ZA_array_off3x2), OP_SVE_D, 0, 0), + SME2p1_INSN ("zero", 0xc00d0000, 0xffff9ffc, sme2_movaz, 0, OP1 (SME_ZA_array_off2x2), OP_SVE_D, F_OD (2) | F_VG_REQ, 0), + SME2p1_INSN ("zero", 0xc00d8000, 0xffff9ffc, sme2_movaz, 0, OP1 (SME_ZA_array_off2x2), OP_SVE_D, F_OD (4) | F_VG_REQ, 0), + + /* ZERO (quad-vector). */ + SME2p1_INSN ("zero", 0xc00e8000, 0xffff9ffc, sme2_movaz, 0, OP1 (SME_ZA_array_off2x4), OP_SVE_D, 0, 0), + SME2p1_INSN ("zero", 0xc00f0000, 0xffff9ffe, sme2_movaz, 0, OP1 (SME_ZA_array_off1x4), OP_SVE_D, F_OD (2) | F_VG_REQ, 0), + SME2p1_INSN ("zero", 0xc00f8000, 0xffff9ffe, sme2_movaz, 0, OP1 (SME_ZA_array_off1x4), OP_SVE_D, F_OD (4) | F_VG_REQ, 0), + /* SVE2p1 Instructions. */ SVE2p1_INSN("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0), SVE2p1_INSN("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0), |