diff options
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/config/tc-i386.c | 10 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 9 | ||||
| -rw-r--r-- | opcodes/i386-gen.c | 2 | ||||
| -rw-r--r-- | opcodes/i386-opc.h | 6 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 20 |
6 files changed, 35 insertions, 17 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 53c1751..fe622f8 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2018-05-07 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (process_suffix): Check addrprefixopreg + instead of addrprefixop0. + 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com> * config/tc-ppc.c (ppc_setup_opcodes) <powerpc_opcodes>: Rewrite code diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index cd53fa46..b4c93a2 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -5997,14 +5997,18 @@ process_suffix (void) /* Now select between word & dword operations via the operand size prefix, except for instructions that will ignore this prefix anyway. */ - if (i.tm.opcode_modifier.addrprefixop0) + if (i.reg_operands > 0 + && i.types[0].bitfield.reg + && i.tm.opcode_modifier.addrprefixopreg + && (i.tm.opcode_modifier.immext + || i.operands == 1)) { /* The address size override prefix changes the size of the first operand. */ if ((flag_code == CODE_32BIT - && i.op->regs[0].reg_type.bitfield.word) + && i.op[0].regs->reg_type.bitfield.word) || (flag_code != CODE_32BIT - && i.op->regs[0].reg_type.bitfield.dword)) + && i.op[0].regs->reg_type.bitfield.dword)) if (!add_prefix (ADDR_PREFIX_OPCODE)) return 0; } diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4bf8685..6da4fc0 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,12 @@ +2018-05-07 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with + AddrPrefixOpReg. + * i386-opc.h (AddrPrefixOp0): Renamed to ... + (AddrPrefixOpReg): This. + (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg. + * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg. + 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com> * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned. diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 826aa04..8334c4a 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -618,7 +618,7 @@ static bitfield opcode_modifiers[] = BITFIELD (HLEPrefixOk), BITFIELD (ToDword), BITFIELD (ToQword), - BITFIELD (AddrPrefixOp0), + BITFIELD (AddrPrefixOpReg), BITFIELD (IsPrefix), BITFIELD (ImmExt), BITFIELD (NoRex64), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 58abea6..570da28 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -445,8 +445,8 @@ enum ToDword, /* Convert to QWORD */ ToQword, - /* Address prefix changes operand 0 */ - AddrPrefixOp0, + /* Address prefix changes register operand */ + AddrPrefixOpReg, /* opcode is a prefix */ IsPrefix, /* instruction has extension in 8 bit imm */ @@ -627,7 +627,7 @@ typedef struct i386_opcode_modifier unsigned int repprefixok:1; unsigned int todword:1; unsigned int toqword:1; - unsigned int addrprefixop0:1; + unsigned int addrprefixopreg:1; unsigned int isprefix:1; unsigned int immext:1; unsigned int norex64:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 3580bdc..2382c61 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -1534,9 +1534,9 @@ monitor, 0, 0xf01, 0xc8, 2, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ // address size override prefix can be used to overrride the AX size in // all modes. // Need to ensure only "monitor %eax/%ax,%ecx,%edx" is accepted. -monitor, 3, 0xf01, 0xc8, 2, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoAVX, { Reg16|Reg32, Reg32, Reg32 } +monitor, 3, 0xf01, 0xc8, 2, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOpReg|NoAVX, { Reg16|Reg32, Reg32, Reg32 } // Need to ensure only "monitor %rax/%eax,%rcx,%rdx" is accepted. -monitor, 3, 0xf01, 0xc8, 2, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64|NoAVX, { Reg32|Reg64, Reg64, Reg64 } +monitor, 3, 0xf01, 0xc8, 2, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOpReg|NoRex64|NoAVX, { Reg32|Reg64, Reg64, Reg64 } movddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } movddup, 2, 0xf20f12, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } movshdup, 2, 0xf316, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } @@ -2813,17 +2813,17 @@ rdtscp, 0, 0xf01, 0xf9, 2, CpuRdtscp, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No // AMD Pacifica additions. clgi, 0, 0xf01, 0xdd, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } invlpga, 0, 0xf01, 0xdf, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } -invlpga, 2, 0xf01, 0xdf, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64, Reg32 } +invlpga, 2, 0xf01, 0xdf, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOpReg|NoRex64, { Reg32|Reg64, Reg32 } skinit, 0, 0xf01, 0xde, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } skinit, 1, 0xf01, 0xde, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Reg32 } stgi, 0, 0xf01, 0xdc, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } vmload, 0, 0xf01, 0xda, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } -vmload, 1, 0xf01, 0xda, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64 } +vmload, 1, 0xf01, 0xda, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOpReg|NoRex64, { Reg32|Reg64 } vmmcall, 0, 0xf01, 0xd9, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } vmrun, 0, 0xf01, 0xd8, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } -vmrun, 1, 0xf01, 0xd8, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64 } +vmrun, 1, 0xf01, 0xd8, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOpReg|NoRex64, { Reg32|Reg64 } vmsave, 0, 0xf01, 0xdb, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } -vmsave, 1, 0xf01, 0xdb, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64 } +vmsave, 1, 0xf01, 0xdb, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOpReg|NoRex64, { Reg32|Reg64 } // SSE4a instructions @@ -5748,9 +5748,9 @@ clzero, 0, 0xf01fc, None, 3, CpuCLZERO, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf| // MONITORX/MWAITX instructions monitorx, 0, 0xf01, 0xfa, 2, CpuMWAITX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } // Need to ensure only "monitorx %eax/%ax,%ecx,%edx" is accepted. -monitorx, 3, 0xf01, 0xfa, 2, CpuMWAITX|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0, { Reg16|Reg32, Reg32, Reg32 } +monitorx, 3, 0xf01, 0xfa, 2, CpuMWAITX|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOpReg, { Reg16|Reg32, Reg32, Reg32 } // Need to ensure only "monitorx %rax/%eax,%rcx,%rdx" is accepted. -monitorx, 3, 0xf01, 0xfa, 2, CpuMWAITX|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64, Reg64, Reg64 } +monitorx, 3, 0xf01, 0xfa, 2, CpuMWAITX|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOpReg|NoRex64, { Reg32|Reg64, Reg64, Reg64 } mwaitx, 0, 0xf01, 0xfb, 2, CpuMWAITX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } // Need to ensure only "mwaitx %eax,%ecx,%ebx" is accepted. @@ -5815,8 +5815,8 @@ pconfig, 0, 0x0f01c5, None, 3, CpuPCONFIG, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS // WAITPKG instructions. -umonitor, 1, 0xf30fae, 0x6, 2, CpuWAITPKG|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|AddrPrefixOp0, { Reg16|Reg32 } -umonitor, 1, 0xf30fae, 0x6, 2, CpuWAITPKG|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|AddrPrefixOp0|NoRex64, { Reg32|Reg64 } +umonitor, 1, 0xf30fae, 0x6, 2, CpuWAITPKG|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|AddrPrefixOpReg, { Reg16|Reg32 } +umonitor, 1, 0xf30fae, 0x6, 2, CpuWAITPKG|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|AddrPrefixOpReg|NoRex64, { Reg32|Reg64 } tpause, 1, 0x660fae, 0x6, 2, CpuWAITPKG, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64 } |