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-rw-r--r--gas/ChangeLog14
-rw-r--r--gas/config/tc-arm.c15
-rw-r--r--gas/testsuite/gas/arm/mve-vaddsub-it-bad.d6
-rw-r--r--gas/testsuite/gas/arm/mve-vaddsub-it-bad.l7
-rw-r--r--gas/testsuite/gas/arm/mve-vaddsub-it-bad.s11
-rw-r--r--gas/testsuite/gas/arm/mve-vaddsub-it.d23
-rw-r--r--gas/testsuite/gas/arm/mve-vaddsub-it.s17
-rw-r--r--gas/testsuite/gas/arm/nomve-vaddsub-it.d24
8 files changed, 114 insertions, 3 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index e6b3207..8bc4b3a 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,17 @@
+2020-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ PR 25660
+ * config/tc-arm.c (operand_parse_code): Add OP_RNSDMQR and OP_oRNSDMQ.
+ (parse_operands): Handle new operand codes.
+ (do_neon_dyadic_long): Make shape check accept the scalar variants.
+ (asm_opcode_insns): Fix operand codes for vaddl and vsubl.
+ * testsuite/gas/arm/mve-vaddsub-it.s: New test.
+ * testsuite/gas/arm/mve-vaddsub-it.d: New test.
+ * testsuite/gas/arm/mve-vaddsub-it-bad.s: New test.
+ * testsuite/gas/arm/mve-vaddsub-it-bad.l: New test.
+ * testsuite/gas/arm/mve-vaddsub-it-bad.d: New test.
+ * testsuite/gas/arm/nomve-vaddsub-it.d: New test.
+
2020-03-11 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention x86 assembler options for CVE-2020-0551.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 329a2de..f2a55ab 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7072,6 +7072,8 @@ enum operand_parse_code
OP_RNDMQ, /* Neon double precision (0..31) or MVE vector register. */
OP_RNDMQR, /* Neon double precision (0..31), MVE vector or ARM register.
*/
+ OP_RNSDMQR, /* Neon single or double precision, MVE vector or ARM register.
+ */
OP_RNQ, /* Neon quad precision register */
OP_RNQMQ, /* Neon quad or MVE vector register. */
OP_RVSD, /* VFP single or double precision register */
@@ -7225,6 +7227,8 @@ enum operand_parse_code
OP_oRNSDQ, /* Optional single, double or quad precision vector register */
OP_oRNSDQMQ, /* Optional single, double or quad register or MVE vector
register. */
+ OP_oRNSDMQ, /* Optional single, double register or MVE vector
+ register. */
OP_oSHll, /* LSL immediate */
OP_oSHar, /* ASR immediate */
OP_oSHllar, /* LSL or ASR immediate */
@@ -7421,6 +7425,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
case OP_oRND:
+ case OP_RNSDMQR:
+ po_reg_or_goto (REG_TYPE_VFS, try_rndmqr);
+ break;
+ try_rndmqr:
case OP_RNDMQR:
po_reg_or_goto (REG_TYPE_RN, try_rndmq);
break;
@@ -7486,6 +7494,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
case OP_RVSD_COND:
po_reg_or_goto (REG_TYPE_VFSD, try_cond);
break;
+ case OP_oRNSDMQ:
case OP_RNSDMQ:
po_reg_or_goto (REG_TYPE_NSD, try_mq2);
break;
@@ -19599,7 +19608,7 @@ neon_mixed_length (struct neon_type_el et, unsigned size)
static void
do_neon_dyadic_long (void)
{
- enum neon_shape rs = neon_select_shape (NS_QDD, NS_QQQ, NS_QQR, NS_NULL);
+ enum neon_shape rs = neon_select_shape (NS_QDD, NS_HHH, NS_FFF, NS_DDD, NS_NULL);
if (rs == NS_QDD)
{
if (vfp_or_neon_is_neon (NEON_CHECK_ARCH | NEON_CHECK_CC) == FAIL)
@@ -26542,8 +26551,8 @@ static const struct asm_opcode insns[] =
#define ARM_VARIANT & fpu_neon_ext_v1
mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
mnUF(vabdl, _vabdl, 3, (RNQMQ, RNDMQ, RNDMQ), neon_dyadic_long),
- mnUF(vaddl, _vaddl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
- mnUF(vsubl, _vsubl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
+ mnUF(vaddl, _vaddl, 3, (RNSDQMQ, oRNSDMQ, RNSDMQR), neon_dyadic_long),
+ mnUF(vsubl, _vsubl, 3, (RNSDQMQ, oRNSDMQ, RNSDMQR), neon_dyadic_long),
mnUF(vand, _vand, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
mnUF(vbic, _vbic, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
diff --git a/gas/testsuite/gas/arm/mve-vaddsub-it-bad.d b/gas/testsuite/gas/arm/mve-vaddsub-it-bad.d
new file mode 100644
index 0000000..1889c21
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vaddsub-it-bad.d
@@ -0,0 +1,6 @@
+#name: Bad MVE vadd/vsub instructions in IT blocks
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vaddsub-it-bad.l
+
+.*: +file format .*arm.*
+
diff --git a/gas/testsuite/gas/arm/mve-vaddsub-it-bad.l b/gas/testsuite/gas/arm/mve-vaddsub-it-bad.l
new file mode 100644
index 0000000..5f41bce
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vaddsub-it-bad.l
@@ -0,0 +1,7 @@
+[^:]*: Assembler messages:
+[^:]*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+[^:]*:5: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+[^:]*:7: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+[^:]*:8: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+[^:]*:10: Error: selected FPU does not support instruction -- `vaddl.s8 q0,d1,d2'
+[^:]*:11: Error: selected FPU does not support instruction -- `vsubl.s8 q0,d1,d2'
diff --git a/gas/testsuite/gas/arm/mve-vaddsub-it-bad.s b/gas/testsuite/gas/arm/mve-vaddsub-it-bad.s
new file mode 100644
index 0000000..180f939
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vaddsub-it-bad.s
@@ -0,0 +1,11 @@
+.syntax unified
+.text
+itt le
+vaddle.f16 s3, s5, s7
+vsuble.f16 s7, s4, s6
+itt lt
+vaddlt.f16 s0, s5, s7
+vsublt.f16 s7, s4, s6
+
+vaddl.s8 q0, d1, d2
+vsubl.s8 q0, d1, d2
diff --git a/gas/testsuite/gas/arm/mve-vaddsub-it.d b/gas/testsuite/gas/arm/mve-vaddsub-it.d
new file mode 100644
index 0000000..e0842b7
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vaddsub-it.d
@@ -0,0 +1,23 @@
+# name: Armv8.1-M Mainline vadd/vsub instructions in it blocks (with MVE)
+# as: -march=armv8.1-m.main+mve.fp+fp.dp
+# objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+[^>]*> bfdc itt le
+[^>]*> ee72 1aa3 vaddle.f32 s3, s5, s7
+[^>]*> ee34 7b06 vaddle.f64 d7, d4, d6
+[^>]*> bfbc itt lt
+[^>]*> ee72 1aa3 vaddlt.f32 s3, s5, s7
+[^>]*> ee34 7b06 vaddlt.f64 d7, d4, d6
+[^>]*> bfdc itt le
+[^>]*> ee72 1ae3 vsuble.f32 s3, s5, s7
+[^>]*> ee34 7b46 vsuble.f64 d7, d4, d6
+[^>]*> bfbc itt lt
+[^>]*> ee72 1ae3 vsublt.f32 s3, s5, s7
+[^>]*> ee34 7b46 vsublt.f64 d7, d4, d6
+[^>]*> bfdc itt le
+[^>]*> ee30 0a06 vaddle.f32 s0, s0, s12
+[^>]*> ee30 0b41 vsuble.f64 d0, d0, d1
+#...
diff --git a/gas/testsuite/gas/arm/mve-vaddsub-it.s b/gas/testsuite/gas/arm/mve-vaddsub-it.s
new file mode 100644
index 0000000..f086a73
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vaddsub-it.s
@@ -0,0 +1,17 @@
+.syntax unified
+.text
+itt le
+vaddle.f32 s3, s5, s7
+vaddle.f64 d7, d4, d6
+itt lt
+vaddlt.f32 s3, s5, s7
+vaddlt.f64 d7, d4, d6
+itt le
+vsuble.f32 s3, s5, s7
+vsuble.f64 d7, d4, d6
+itt lt
+vsublt.f32 s3, s5, s7
+vsublt.f64 d7, d4, d6
+itt le
+vaddle.f32 s0, s12
+vsuble.f64 d0, d1
diff --git a/gas/testsuite/gas/arm/nomve-vaddsub-it.d b/gas/testsuite/gas/arm/nomve-vaddsub-it.d
new file mode 100644
index 0000000..50b12a0
--- /dev/null
+++ b/gas/testsuite/gas/arm/nomve-vaddsub-it.d
@@ -0,0 +1,24 @@
+# name: Armv8.1-M Mainline vadd/vsub instructions in it blocks (without MVE)
+# as: -march=armv8.1-m.main+fp.dp
+# source: mve-vaddsub-it.s
+# objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+[^>]*> bfdc itt le
+[^>]*> ee72 1aa3 vaddle.f32 s3, s5, s7
+[^>]*> ee34 7b06 vaddle.f64 d7, d4, d6
+[^>]*> bfbc itt lt
+[^>]*> ee72 1aa3 vaddlt.f32 s3, s5, s7
+[^>]*> ee34 7b06 vaddlt.f64 d7, d4, d6
+[^>]*> bfdc itt le
+[^>]*> ee72 1ae3 vsuble.f32 s3, s5, s7
+[^>]*> ee34 7b46 vsuble.f64 d7, d4, d6
+[^>]*> bfbc itt lt
+[^>]*> ee72 1ae3 vsublt.f32 s3, s5, s7
+[^>]*> ee34 7b46 vsublt.f64 d7, d4, d6
+[^>]*> bfdc itt le
+[^>]*> ee30 0a06 vaddle.f32 s0, s0, s12
+[^>]*> ee30 0b41 vsuble.f64 d0, d0, d1
+#...
generated by cgit v1.1 at 2024-09-08 22:29:04 +0000