diff options
| -rw-r--r-- | gas/NEWS | 2 | ||||
| -rw-r--r-- | gas/config/tc-aarch64.c | 2 | ||||
| -rw-r--r-- | gas/doc/c-aarch64.texi | 2 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 1 |
4 files changed, 7 insertions, 0 deletions
@@ -1,5 +1,7 @@ -*- text -*- +* Add SME2 support to the AArch64 port. + Changes in 2.40: * Add support for Intel RAO-INT instructions. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 2d4c610..6ebfcda 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -10183,6 +10183,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)}, {"sme-i16i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64, 0), AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)}, + {"sme2", AARCH64_FEATURE (AARCH64_FEATURE_SME2, 0), + AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)}, {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16, 0), AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)}, {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM, 0), diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 3921c0d..acde4a7 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -235,6 +235,8 @@ automatically cause those extensions to be disabled. @tab Enable SME F64F64 Extension. @item @code{sme-i16i64} @tab Armv9-A @tab No @tab Enable SME I16I64 Extension. +@item @code{sme2} @tab Armv9-A @tab No + @tab Enable SME2. This implies @code{sme}. @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later @tab Enable Speculative Store Bypassing Safe state read and write. @item @code{sve} @tab ARMv8.2-A @tab Armv9-A or later diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index ef59d53..5c9b5e5 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -100,6 +100,7 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_SME_I16I64 (1ULL << 58) /* SME I16I64. */ #define AARCH64_FEATURE_V8_8 (1ULL << 59) /* Armv8.8 processors. */ #define AARCH64_FEATURE_CSSC (1ULL << 60) /* Common Short Sequence Compression instructions. */ +#define AARCH64_FEATURE_SME2 (1ULL << 61) /* SME2. */ /* Crypto instructions are the combination of AES and SHA2. */ #define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES) |