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-rw-r--r--gas/ChangeLog6
-rw-r--r--gas/config/tc-mcore.c64
-rw-r--r--opcodes/ChangeLog8
-rw-r--r--opcodes/mcore-dis.c14
-rw-r--r--opcodes/mcore-opc.h4
5 files changed, 1 insertions, 95 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index e1766bb..e706ef0 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,9 +1,3 @@
-1999-10-25 Nick Clifton <nickc@cygnus.com>
-
- * config/tc-mcore.c (parse_psrmod): New function: Parse the psr
- flag specifiers of a psrclr/psrset instruction.
- (md_assemble): Parse instructions of class OPSR.
-
Mon Oct 18 18:11:10 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
* tc_d10v.c (find_opcode): Allow ATSIGN to match expressions of the
diff --git a/gas/config/tc-mcore.c b/gas/config/tc-mcore.c
index 549b43d..a83b46e 100644
--- a/gas/config/tc-mcore.c
+++ b/gas/config/tc-mcore.c
@@ -48,7 +48,6 @@ static char * parse_exp PARAMS ((char *, expressionS *));
static char * parse_rt PARAMS ((char *, char **, int, expressionS *));
static char * parse_imm PARAMS ((char *, unsigned *, unsigned, unsigned));
static char * parse_mem PARAMS ((char *, unsigned *, unsigned *, unsigned));
-static char * parse_psrmod PARAMS ((char *, unsigned *));
static void make_name PARAMS ((char *, char *, int));
static int enter_literal PARAMS ((expressionS *, int));
static void dump_literals PARAMS ((int));
@@ -590,46 +589,6 @@ parse_creg (s, reg)
}
static char *
-parse_psrmod (s, reg)
- char * s;
- unsigned * reg;
-{
- int i;
- char buf[10];
- static struct psrmods
- {
- char * name;
- unsigned int value;
- }
- psrmods[] =
- {
- { "ie", 1 },
- { "fe", 2 },
- { "ee", 4 },
- { "af", 8 } /* really 0 and non-combinable */
- };
-
- for (i = 0; i < 2; i++)
- buf[i] = isascii (s[i]) ? tolower (s[i]) : 0;
-
- for (i = sizeof (psrmods) / sizeof (psrmods[0]); i--;)
- {
- if (! strncmp (psrmods[i].name, buf, 2))
- {
- * reg = psrmods[i].value;
-
- return s + 2;
- }
- }
-
- as_bad (_("bad/missing psr specifier"));
-
- * reg = 0;
-
- return s;
-}
-
-static char *
parse_exp (s, e)
char * s;
expressionS * e;
@@ -1635,29 +1594,6 @@ md_assemble (str)
output = frag_more (2);
break;
- case OPSR:
- op_end = parse_psrmod (op_end + 1, & reg);
-
- /* Look for further selectors. */
- while (* op_end == ',')
- {
- unsigned value;
-
- op_end = parse_psrmod (op_end + 1, & value);
-
- if (value & reg)
- as_bad (_("duplicated psr bit specifier"));
-
- reg |= value;
- }
-
- if (reg > 8)
- as_bad (_("`af' must appear alone"));
-
- inst |= (reg & 0x7);
- output = frag_more (2);
- break;
-
default:
as_bad (_("unimplemented opcode \"%s\""), name);
}
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9160f9e..c4f4045 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,11 +1,3 @@
-1999-10-25 Nick Clifton <nickc@cygnus.com>
-
- * mcore-opc.h (enum mcore_opclass): Add class OPSR.
- (mcore_table): Add psrclr and psrset instructions.
-
- * mcore-dis.c (array imsk): Add mask for OPSR class.
- (print_insn_mcore): Add decode for OPSR class insns.
-
1999-10-18 Michael Meissner <meissner@cygnus.com>
* alpha-opc.c (alpha_operands): Fill in missing initializer.
diff --git a/opcodes/mcore-dis.c b/opcodes/mcore-dis.c
index 2c9f041..957a01a 100644
--- a/opcodes/mcore-dis.c
+++ b/opcodes/mcore-dis.c
@@ -101,8 +101,6 @@ static const unsigned short imsk[] =
/* OMc */ 0xFF00,
/* SIa */ 0xFE00,
- /* OPSR */ 0xFFF8, /* psrset/psrclr */
-
/* JC */ 0, /* JC,JU,JL don't appear in object */
/* JU */ 0,
/* JL */ 0,
@@ -283,18 +281,6 @@ print_insn_mcore (memaddr, info)
}
break;
- case OPSR:
- {
- static char * fields[] =
- {
- "af", "ie", "fe", "fe,ie",
- "ee", "ee,ie", "ee,fe", "ee,fe,ie"
- };
-
- fprintf (stream, "\t%s", fields[inst & 0x7]);
- }
- break;
-
default:
/* if the disassembler lags the instruction set */
fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
diff --git a/opcodes/mcore-opc.h b/opcodes/mcore-opc.h
index 208b881..606ba84 100644
--- a/opcodes/mcore-opc.h
+++ b/opcodes/mcore-opc.h
@@ -23,7 +23,7 @@ typedef enum
O0, OT, O1, OC, O2, X1, OI, OB,
OMa, SI, I7, LS, BR, BL, LR, LJ,
RM, RQ, JSR, JMP, OBRa, OBRb, OBRc, OBR2,
- O1R1, OMb, OMc, SIa, OPSR,
+ O1R1, OMb, OMc, SIa,
JC, JU, JL, RSI, DO21, OB2
}
mcore_opclass;
@@ -99,8 +99,6 @@ mcore_opcode_info mcore_table[] =
{ "tst", O2, 0, 0x0E00 },
{ "cmpne", O2, 0, 0x0F00 },
{ "mfcr", OC, 0, 0x1000 },
- { "psrclr", OPSR, 0, 0x11F0 },
- { "psrset", OPSR, 0, 0x11F8 },
{ "mov", O2, 0, 0x1200 },
{ "bgenr", O2, 0, 0x1300 },
{ "rsub", O2, 0, 0x1400 },