diff options
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/arc-regs.h | 3 |
2 files changed, 6 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 73091b9..5d83578 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2020-02-25 Claudiu Zissulescu <claziss@gmail.com> + + * arc-regs.h (int_vector_base): Make it available for all ARC + CPUs. + 2020-02-20 Nelson Chu <nelson.chu@sifive.com> * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is diff --git a/opcodes/arc-regs.h b/opcodes/arc-regs.h index a1d98bf..4494a06 100644 --- a/opcodes/arc-regs.h +++ b/opcodes/arc-regs.h @@ -71,8 +71,7 @@ DEF (0x21, ARC_OPCODE_ARCALL, NONE, count0) DEF (0x22, ARC_OPCODE_ARCALL, NONE, control0) DEF (0x23, ARC_OPCODE_ARCALL, NONE, limit0) DEF (0x24, ARC_OPCODE_ARCV1, NONE, pcport) -DEF (0x25, ARC_OPCODE_ARC700, NONE, int_vector_base) -DEF (0x25, ARC_OPCODE_ARCV2, NONE, int_vector_base) +DEF (0x25, ARC_OPCODE_ARCALL, NONE, int_vector_base) DEF (0x26, ARC_OPCODE_ARC600, NONE, aux_vbfdw_mode) DEF (0x27, ARC_OPCODE_ARC600, NONE, aux_vbfdw_bm0) DEF (0x28, ARC_OPCODE_ARC600, NONE, aux_vbfdw_bm1) |