diff options
| -rw-r--r-- | gas/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/ppc/e500mc.d | 4 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 4 |
4 files changed, 14 insertions, 4 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 18305c6..99ea036 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2009-02-19 Peter Bergner <bergner@vnet.ibm.com> + + * gas/ppc/e500mc.d ("lfdepx", "stfdepx"): Fix tests to expect a + floating point register. + 2009-02-18 Adam Nemet <anemet@caviumnetworks.com> * gas/mips/octeon.s: Add more tests for dmfc2 and dmtc2. diff --git a/gas/testsuite/gas/ppc/e500mc.d b/gas/testsuite/gas/ppc/e500mc.d index 4ffaba8..aeee31d 100644 --- a/gas/testsuite/gas/ppc/e500mc.d +++ b/gas/testsuite/gas/ppc/e500mc.d @@ -22,12 +22,12 @@ Disassembly of section \.text: 30: 7c 85 32 3e lhepx r4,r5,r6 34: 7c e8 48 3e lwepx r7,r8,r9 38: 7d 4b 60 3a ldepx r10,r11,r12 - 3c: 7d ae 7c be lfdepx r13,r14,r15 + 3c: 7d ae 7c be lfdepx f13,r14,r15 40: 7e 11 91 be stbepx r16,r17,r18 44: 7e 74 ab 3e sthepx r19,r20,r21 48: 7e d7 c1 3e stwepx r22,r23,r24 4c: 7f 3a d9 3a stdepx r25,r26,r27 - 50: 7f 9d f5 be stfdepx r28,r29,r30 + 50: 7f 9d f5 be stfdepx f28,r29,r30 54: 7c 01 14 06 lbdx r0,r1,r2 58: 7d 8d 74 46 lhdx r12,r13,r14 5c: 7c 64 2c 86 lwdx r3,r4,r5 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index db66f45..d1a0ada 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2009-02-19 Peter Bergner <bergner@vnet.ibm.com> + + * ppc-opc.c (powerpc_opcodes) <"lfdepx", "stfdepx">: Fix the first + operand to be a float point register (FRT/FRS). + 2009-02-18 Adam Nemet <anemet@caviumnetworks.com> * mips-opc.c (mips_builtin_opcodes): Move the Octeon-specific diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 5ce87b7..294af73 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -4286,7 +4286,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lfdx", X(31,599), X_MASK, COM, PPCNONE, {FRT, RA0, RB}}, -{"lfdepx", X(31,607), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, +{"lfdepx", X(31,607), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}}, {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, PPCNONE, {FRT, RB}}, {"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, @@ -4373,7 +4373,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"sreq", XRC(31,729,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, {"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, -{"stfdepx", X(31,735), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, +{"stfdepx", X(31,735), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}}, {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, PPCNONE, {RT, FRB}}, {"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, |