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| author | Mike Frysinger <vapier@gentoo.org> | 2015-04-02 20:15:43 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2015-04-02 20:40:11 -0400 |
| commit | b366059a5b384ed822e44a6407b35ab1386b925f (patch) | |
| tree | 8e30b6bbd9b448481fc187c3cef33d2d71938c90 /sim | |
| parent | ef6f73553efece92e797b138cf02aaacce19574a (diff) | |
| download | gdb-b366059a5b384ed822e44a6407b35ab1386b925f.zip gdb-b366059a5b384ed822e44a6407b35ab1386b925f.tar.gz gdb-b366059a5b384ed822e44a6407b35ab1386b925f.tar.bz2 | |
sim: d10v: fix signal updates
Way back in aba6488e0b73756f31f154d12a228baa82a68d8a, a bunch of signal
defines were changed to TARGET_SIGNAL_xxx. For d10v, the transition was
incomplete which lead to sim_stop_reason using the new set but sim_resume
still using the old set. Which meant in some cases, the sim would never
actually stop.
Convert all the remaining SIGxxx defines in here to TARGET_SIGNAL_xxx.
This has the nice side effect of fixing the testsuite.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/d10v/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/d10v/interp.c | 13 |
2 files changed, 11 insertions, 8 deletions
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index e34b918..e09a14f 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -1,3 +1,9 @@ +2015-04-02 Mike Frysinger <vapier@gentoo.org> + + * interp.c (lookup_hash): Change SIGILL to GDB_SIGNAL_ILL. + (sim_resume): Change SIGBUS/SIGSEGV to GDB_SIGNAL_BUS, SIGILL to + GDB_SIGNAL_ILL, and SIGTRAP to GDB_SIGNAL_TRAP. + 2015-04-01 Mike Frysinger <vapier@gentoo.org> * interp.c (sim_set_profile, sim_set_profile_size): Delete. diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c index 1aae3e4..7fc0745 100644 --- a/sim/d10v/interp.c +++ b/sim/d10v/interp.c @@ -80,7 +80,7 @@ lookup_hash (uint32 ins, int size) { if (h->next == NULL) { - State.exception = SIGILL; + State.exception = GDB_SIGNAL_ILL; State.pc_changed = 1; /* Don't increment the PC. */ return NULL; } @@ -936,17 +936,14 @@ sim_resume (SIM_DESC sd, int step, int siggnal) { case 0: break; -#ifdef SIGBUS - case SIGBUS: -#endif - case SIGSEGV: + case GDB_SIGNAL_BUS: SET_BPC (PC); SET_BPSW (PSW); SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); JMP (AE_VECTOR_START); SLOT_FLUSH (); break; - case SIGILL: + case GDB_SIGNAL_ILL: SET_BPC (PC); SET_BPSW (PSW); SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); @@ -963,7 +960,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal) iaddr = imem_addr ((uint32)PC << 2); if (iaddr == State.mem.fault) { - State.exception = SIGBUS; + State.exception = GDB_SIGNAL_BUS; break; } @@ -1035,7 +1032,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal) while ( !State.exception && !stop_simulator); if (step && !State.exception) - State.exception = SIGTRAP; + State.exception = GDB_SIGNAL_TRAP; } void |