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| author | Anthony Green <green@redhat.com> | 2012-09-08 01:26:07 +0000 |
|---|---|---|
| committer | Anthony Green <green@redhat.com> | 2012-09-08 01:26:07 +0000 |
| commit | 78ca4e81ffc025ba2f18ab6964a84d6693624b5d (patch) | |
| tree | 09292ca24360eeb8c0867d9eda7f9b45a45acd80 /sim | |
| parent | 7078b4097f41309449124a390858941c41cc1c89 (diff) | |
| download | gdb-78ca4e81ffc025ba2f18ab6964a84d6693624b5d.zip gdb-78ca4e81ffc025ba2f18ab6964a84d6693624b5d.tar.gz gdb-78ca4e81ffc025ba2f18ab6964a84d6693624b5d.tar.bz2 | |
Adjust for branch target encoding change
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/moxie/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/moxie/interp.c | 20 |
2 files changed, 15 insertions, 10 deletions
diff --git a/sim/moxie/ChangeLog b/sim/moxie/ChangeLog index d4f1e24..ddab6e9 100644 --- a/sim/moxie/ChangeLog +++ b/sim/moxie/ChangeLog @@ -1,3 +1,8 @@ +2012-09-07 Anthony Green <green@moxielogic.com> + + * interp.c (sim_resume): Branches are now relative to the + address of the instruction following the branch. + 2012-06-17 Mike Frysinger <vapier@gentoo.org> * interp.c: Include config.h first. Also include fcntl.h directly. diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c index c16c34f..b8edc10 100644 --- a/sim/moxie/interp.c +++ b/sim/moxie/interp.c @@ -290,69 +290,69 @@ sim_resume (sd, step, siggnal) { TRACE("beq"); if (cpu.asregs.cc & CC_EQ) - pc += INST2OFFSET(inst) - 2; + pc += INST2OFFSET(inst); } break; case 0x01: /* bne */ { TRACE("bne"); if (! (cpu.asregs.cc & CC_EQ)) - pc += INST2OFFSET(inst) - 2; + pc += INST2OFFSET(inst); } break; case 0x02: /* blt */ { TRACE("blt"); if (cpu.asregs.cc & CC_LT) - pc += INST2OFFSET(inst) - 2; + pc += INST2OFFSET(inst); } break; case 0x03: /* bgt */ { TRACE("bgt"); if (cpu.asregs.cc & CC_GT) - pc += INST2OFFSET(inst) - 2; + pc += INST2OFFSET(inst); } break; case 0x04: /* bltu */ { TRACE("bltu"); if (cpu.asregs.cc & CC_LTU) - pc += INST2OFFSET(inst) - 2; + pc += INST2OFFSET(inst); } break; case 0x05: /* bgtu */ { TRACE("bgtu"); if (cpu.asregs.cc & CC_GTU) - pc += INST2OFFSET(inst) - 2; + pc += INST2OFFSET(inst); } break; case 0x06: /* bge */ { TRACE("bge"); if (cpu.asregs.cc & (CC_GT | CC_EQ)) - pc += INST2OFFSET(inst) - 2; + pc += INST2OFFSET(inst); } break; case 0x07: /* ble */ { TRACE("ble"); if (cpu.asregs.cc & (CC_LT | CC_EQ)) - pc += INST2OFFSET(inst) - 2; + pc += INST2OFFSET(inst); } break; case 0x08: /* bgeu */ { TRACE("bgeu"); if (cpu.asregs.cc & (CC_GTU | CC_EQ)) - pc += INST2OFFSET(inst) - 2; + pc += INST2OFFSET(inst); } break; case 0x09: /* bleu */ { TRACE("bleu"); if (cpu.asregs.cc & (CC_LTU | CC_EQ)) - pc += INST2OFFSET(inst) - 2; + pc += INST2OFFSET(inst); } break; default: |