For instructions moved into v850.igen was computing (wrong) NIA when

this wasn't needed.

4 files changed, 28 insertions, 14 deletions

diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index 7a99f99..2785dc9 100644
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,3 +1,10 @@
+Tue Sep 16 09:02:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* Makefile.in (semantics.o): Add dependency.
+
+	* sim-main.h (SAVE_1, SAVE_2): Perform backward compatible save,
+ 	do not adjust CIA/NIA.
+
 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
 start-sanitize-v850eq
diff --git a/sim/v850/Makefile.in b/sim/v850/Makefile.in
index 723d224..c7125a6 100644
--- a/sim/v850/Makefile.in
+++ b/sim/v850/Makefile.in
@@ -155,3 +155,4 @@ clean-extra: clean-igen
 #interp.o: interp.c table.c $(INCLUDE)
 simops.o: simops.c $(INCLUDE)
 #table.o: table.c
+semantics.o: $(INCLUDE)
diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h
index 2cab082..d222282 100644
--- a/sim/v850/sim-main.h
+++ b/sim/v850/sim-main.h
@@ -96,21 +96,27 @@ OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 */
 OP[3] = inst;
 #endif
 
-#define COMPAT_1(CALL) \
+#define SAVE_1 \
 PC = cia; \
 OP[0] = instruction_0 & 0x1f; \
 OP[1] = (instruction_0 >> 11) & 0x1f; \
 OP[2] = 0; \
-OP[3] = instruction_0 ; \
+OP[3] = instruction_0
+
+#define COMPAT_1(CALL) \
+SAVE_1; \
 PC += (CALL); \
 nia = PC
 
-#define COMPAT_2(CALL) \
+#define SAVE_2 \
 PC = cia; \
 OP[0] = instruction_0 & 0x1f; \
 OP[1] = (instruction_0 >> 11) & 0x1f; \
 OP[2] = instruction_1; \
-OP[3] = (instruction_1 << 16) | instruction_0; \
+OP[3] = (instruction_1 << 16) | instruction_0
+
+#define COMPAT_2(CALL) \
+SAVE_2; \
 PC += (CALL); \
 nia = PC
 
diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen
index 713f96a..b938b0a 100644
--- a/sim/v850/v850.igen
+++ b/sim/v850/v850.igen
@@ -475,7 +475,7 @@ rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 00000000011,RRRRR:I:::jmp
 "jmp [r<reg1>]"
 {
-  COMPAT_1 (0);
+  SAVE_1;
   trace_input ("jmp", OP_REG, 0);
   nia = State.regs[ reg1 ];
   trace_output (OP_REG);
@@ -738,7 +738,7 @@ rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 "prepare <list12>, <imm5>"
 {
   int  i;
-  COMPAT_2 (0);
+  SAVE_2;
   
   trace_input ("prepare", OP_PUSHPOP1, 0);
   
@@ -967,7 +967,7 @@ rrrrr!0,0000110,dddd:IV:::sld.bu
 {
   unsigned long result;
       
-  COMPAT_1 (0);
+  SAVE_1;
   result = load_mem (State.regs[30] + disp4, 1);
       
   /* start-sanitize-v850eq */
@@ -1181,7 +1181,7 @@ rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
 // end-sanitize-v850eq
 "zxb r<reg1>"
 {
-  COMPAT_1 (0);
+  SAVE_1;
 
   trace_input ("zxb", OP_REG, 0);
 
@@ -1202,7 +1202,7 @@ rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
 // end-sanitize-v850eq
 "zxh r<reg1>"
 {
-  COMPAT_1 (0);
+  SAVE_1;
 
   trace_input ("zxh", OP_REG, 0);
       
@@ -1232,7 +1232,7 @@ rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
   signed32 divide_by;
   signed32 divide_this;
   boolean overflow = false;
-  COMPAT_2 (0);
+  SAVE_2;
       
   trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
 
@@ -1266,7 +1266,7 @@ rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
   signed32 divide_by;
   signed32 divide_this;
   boolean overflow = false;
-  COMPAT_2 (0);
+  SAVE_2;
       
   trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
   
@@ -1300,7 +1300,7 @@ rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
   signed32 divide_by;
   signed32 divide_this;
   boolean overflow = false;
-  COMPAT_2 (0);
+  SAVE_2;
       
   trace_input ("divn", OP_IMM_REG_REG_REG, 0);
 
@@ -1334,7 +1334,7 @@ rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
   signed32 divide_by;
   signed32 divide_this;
   boolean overflow = false;
-  COMPAT_2 (0);
+  SAVE_2;
 
   trace_input ("divun", OP_IMM_REG_REG_REG, 0);
 
@@ -1404,7 +1404,7 @@ rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
 "pushml <list18>"
 {
   int i;
-  COMPAT_2 (0);
+  SAVE_2;
   
   trace_input ("pushml", OP_PUSHPOP3, 0);