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authorDJ Delorie <dj@redhat.com>2008-02-06 04:41:26 +0000
committerDJ Delorie <dj@redhat.com>2008-02-06 04:41:26 +0000
commit98e460c30d2f5e3848d7ae429bebcce3b8c90b81 (patch)
tree40dbef44e0edc002f1f39fd3fd7f5efd0d32a8a3 /sim/v850/v850.igen
parent1a4ca44aeb9dbeed9848d1703a3c4ddae5cb6ffe (diff)
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* simops.c (OP_1C007E0): Compensate for 64 bit hosts.
(OP_18007E0): Likewise. (OP_2C007E0): Likewise. (OP_28007E0): Likewise. * v850.igen (divh): Likewise.
Diffstat (limited to 'sim/v850/v850.igen')
-rw-r--r--sim/v850/v850.igen4
1 files changed, 2 insertions, 2 deletions
diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen
index 6617bd8..c0382bc 100644
--- a/sim/v850/v850.igen
+++ b/sim/v850/v850.igen
@@ -356,7 +356,7 @@ rrrrr!0,000010,RRRRR!0:I:::divh
op0 = EXTEND16 (State.regs[OP[0]]);
op1 = State.regs[OP[1]];
- if (op0 == 0xffffffff && op1 == 0x80000000)
+ if (op0 == -1 && op1 == 0x80000000)
{
PSW &= ~PSW_Z;
PSW |= PSW_OV | PSW_S;
@@ -368,7 +368,7 @@ rrrrr!0,000010,RRRRR!0:I:::divh
}
else
{
- result = op1 / op0;
+ result = (signed32) op1 / op0;
ov = 0;
/* Compute the condition codes. */