Add support to count the number of instructions issued.

1 files changed, 187 insertions, 0 deletions

diff --git a/sim/ppc/cpu.h b/sim/ppc/cpu.h
new file mode 100644
index 0000000..f9790e8
--- /dev/null
+++ b/sim/ppc/cpu.h
@@ -0,0 +1,187 @@
+/*  This file is part of the program psim.
+
+    Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+ 
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ 
+    */
+
+
+#ifndef _CPU_H_
+#define _CPU_H_
+
+#ifndef INLINE_CPU
+#define INLINE_CPU
+#endif
+
+#include "basics.h"
+#include "registers.h"
+#include "device_tree.h"
+#include "memory_map.h"
+#include "core.h"
+#include "vm.h"
+#include "events.h"
+#include "interrupts.h"
+#include "psim.h"
+#include "icache.h"
+
+
+/* typedef struct _cpu cpu;
+
+   Declared in basics.h because it is used opaquely throughout the
+   code */
+
+
+/* Create a cpu object */
+
+INLINE_CPU cpu *cpu_create
+(psim *system,
+ core *memory,
+ event_queue *events,
+ int cpu_nr);
+
+
+/* Find our way home */
+
+INLINE_CPU psim *cpu_system
+(cpu *processor);
+
+INLINE_CPU int cpu_nr
+(cpu *processor);
+
+INLINE_CPU event_queue *cpu_event_queue
+(cpu *processor);
+
+
+/* The processors local concept of time */
+
+INLINE_CPU signed64 cpu_get_time_base
+(cpu *processor);
+
+INLINE_CPU void cpu_set_time_base
+(cpu *processor,
+ signed64 time_base);
+
+INLINE_CPU signed32 cpu_get_decrementer
+(cpu *processor);
+
+INLINE_CPU void cpu_set_decrementer
+(cpu *processor,
+ signed32 decrementer);
+
+
+/* manipulate the program counter
+
+   The program counter is not included in the register file.  Instead
+   it is extracted and then later restored (set, reset, halt).  This
+   is to give the user of the cpu (and the compiler) the chance to
+   minimize the need to load/store the cpu's PC value.  (Especially in
+   the case of a single processor) */
+
+INLINE_CPU void cpu_set_program_counter
+(cpu *processor,
+ unsigned_word new_program_counter);
+
+INLINE_CPU unsigned_word cpu_get_program_counter
+(cpu *processor);
+
+INLINE_CPU void cpu_restart
+(cpu *processor,
+ unsigned_word nia);
+
+INLINE_CPU void cpu_halt
+(cpu *processor,
+ unsigned_word nia,
+ stop_reason reason,
+ int signal);
+
+
+#if WITH_IDECODE_CACHE
+/* gain acces to the processors instruction cracking cache
+
+   Only useful (and visable) if we're cracking the cache */
+INLINE_CPU idecode_cache *cpu_icache
+(cpu *processor);
+#endif
+
+
+/* reveal the processor address maps
+
+   At first sight it may seem better to, instead of exposing the cpu's
+   inner vm maps, to have the cpu its self provide memory manipulation
+   functions. (eg cpu_instruction_fetch() cpu_data_read_4())
+
+   Unfortunatly in addition to these functions is the need (for the
+   debugger) to be able to read/write to memory in ways that violate
+   the vm protection (eg store breakpoint instruction in the
+   instruction map). */
+
+INLINE_CPU vm_instruction_map *cpu_instruction_map
+(cpu *processor);
+
+INLINE_CPU vm_data_map *cpu_data_map
+(cpu *processor);
+
+INLINE_CPU core *cpu_core
+(cpu *processor);
+
+
+/* grant access to the reservation information */
+typedef struct _memory_reservation {
+  int valid;
+  unsigned_word addr;
+  unsigned_word data;
+} memory_reservation;
+
+INLINE_CPU memory_reservation *cpu_reservation
+(cpu *processor);
+
+
+INLINE_CPU void cpu_increment_number_of_insns
+(cpu *processor);
+
+INLINE_CPU long cpu_get_number_of_insns
+(cpu *processor);
+
+INLINE_CPU void cpu_print_info
+(cpu *processor,
+ int verbose);
+
+/* Registers:
+
+   This model exploits the PowerPC's requirement for a synchronization
+   to occure after (or before) the update of any context controlling
+   register.  All context sync points must call the sync function
+   below to when ever a synchronization point is reached */
+
+INLINE_CPU registers *cpu_registers
+(cpu *processor);
+
+INLINE_CPU void cpu_synchronize_context
+(cpu *processor);
+
+#define IS_PROBLEM_STATE(PROCESSOR) \
+(CURRENT_ENVIRONMENT == VIRTUAL_ENVIRONMENT \
+ || (cpu_registers(PROCESSOR)->msr & msr_problem_state))
+
+#define IS_64BIT_MODE(PROCESSOR) \
+((CURRENT_ENVIRONMENT == VIRTUAL_ENVIRONMENT && WITH_64BIT_TARGET) \
+ || (cpu_registers(PROCESSOR)->msr & msr_64bit_mode))
+
+#define IS_FP_AVAILABLE(PROCESSOR) \
+(CURRENT_ENVIRONMENT == VIRTUAL_ENVIRONMENT \
+ || (cpu_registers(PROCESSOR)->msr & msr_floating_point_available))
+
+#endif