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authorChris Demetriou <cgd@google.com>2002-03-08 00:37:14 +0000
committerChris Demetriou <cgd@google.com>2002-03-08 00:37:14 +0000
commit82f728dbb8c6170c01f938b09076fb0992accbf1 (patch)
tree2259b001dca5734f9a45dea7f8bb7e69dcec50f2 /sim/mips
parent6225b4b7fc5b7e3e89857093bd7fef2a6aec2fb7 (diff)
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2002-03-07 Chris Demetriou <cgd@broadcom.com>
* mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print immediate or code as a hex value with the "%#lx" format. (ANDI): Likewise, and fix printed instruction name.
Diffstat (limited to 'sim/mips')
-rw-r--r--sim/mips/ChangeLog6
-rw-r--r--sim/mips/mips.igen12
2 files changed, 12 insertions, 6 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 1a37721..26e49b6 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,9 @@
+2002-03-07 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
+ immediate or code as a hex value with the "%#lx" format.
+ (ANDI): Likewise, and fix printed instruction name.
+
2002-03-05 Chris Demetriou <cgd@broadcom.com>
* sim-main.h (UndefinedResult, Unpredictable): New macros
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index d1a3f1a..d8d4dfa 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -408,7 +408,7 @@
001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
-"and r<RT>, r<RS>, <IMMEDIATE>"
+"andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
@@ -800,7 +800,7 @@
000000,20.CODE,001101:SPECIAL:32::BREAK
-"break <CODE>"
+"break %#lx<CODE>"
*mipsI:
*mipsII:
*mipsIII:
@@ -1775,7 +1775,7 @@
001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
-"lui r<RT>, <IMMEDIATE>"
+"lui r<RT>, %#lx<IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
@@ -2096,7 +2096,7 @@
}
001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
-"ori r<RT>, r<RS>, <IMMEDIATE>"
+"ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
@@ -2736,7 +2736,7 @@
000000,20.CODE,001100:SPECIAL:32::SYSCALL
-"syscall <CODE>"
+"syscall %#lx<CODE>"
*mipsI:
*mipsII:
*mipsIII:
@@ -2948,7 +2948,7 @@
}
001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
-"xori r<RT>, r<RS>, <IMMEDIATE>"
+"xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII: