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authorTom de Vries <tdevries@suse.de>2024-11-23 13:07:38 +0100
committerTom de Vries <tdevries@suse.de>2024-11-23 13:07:38 +0100
commitd2d240ff89b4d3359ea70cdb47d3e79294ca891a (patch)
treed277cf5c4263881d513deb2d7389c2a0c1f4610b /sim/frv
parent8dfa29fcbd60bead4d67569bd14c818540959130 (diff)
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[sim] Run spellcheck.sh in sim (part 1)
Run gdb/contrib/spellcheck.sh on directory sim. Fix auto-corrected typos: ... accessable -> accessible accidently -> accidentally accomodate -> accommodate adress -> address afair -> affair agains -> against agressively -> aggressively annuled -> annulled arbitary -> arbitrary arround -> around auxillary -> auxiliary availablity -> availability clasic -> classic comming -> coming controled -> controlled controling -> controlling destory -> destroy existance -> existence explictly -> explicitly faciliate -> facilitate fouth -> fourth fullfilled -> fulfilled guarentee -> guarantee hinderance -> hindrance independant -> independent inital -> initial loosing -> losing occurance -> occurrence occured -> occurred occuring -> occurring omited -> omitted oportunity -> opportunity parallely -> parallelly permissable -> permissible postive -> positive powerfull -> powerful preceed -> precede preceeding -> preceding preceeds -> precedes primative -> primitive probaly -> probably programable -> programmable propogate -> propagate propper -> proper recieve -> receive reconized -> recognized refered -> referred refering -> referring relevent -> relevant responisble -> responsible retreive -> retrieve safty -> safety specifiying -> specifying spontanous -> spontaneous sqaure -> square successfull -> successful supress -> suppress sytem -> system thru -> through transfered -> transferred trigered -> triggered unfortunatly -> unfortunately upto -> up to usefull -> useful wierd -> weird writen -> written doesnt -> doesn't isnt -> isn't ... Manually undid the "andd -> and" transformation in sim/testsuite/cr16/andd.cgs and sim/cr16/simops.c. Tested by rebuilding on x86_64-linux. Approved-By: Tom Tromey <tom@tromey.com>
Diffstat (limited to 'sim/frv')
-rw-r--r--sim/frv/frv-sim.h2
-rw-r--r--sim/frv/profile.c4
-rw-r--r--sim/frv/traps.c2
3 files changed, 4 insertions, 4 deletions
diff --git a/sim/frv/frv-sim.h b/sim/frv/frv-sim.h
index d6c0912..e504abe 100644
--- a/sim/frv/frv-sim.h
+++ b/sim/frv/frv-sim.h
@@ -266,7 +266,7 @@ enum frv_ec
/* FR-V Interrupt.
This struct contains enough information to describe a particular interrupt
- occurance. */
+ occurrence. */
struct frv_interrupt
{
enum frv_interrupt_kind kind;
diff --git a/sim/frv/profile.c b/sim/frv/profile.c
index 6903a1b..1f63549 100644
--- a/sim/frv/profile.c
+++ b/sim/frv/profile.c
@@ -598,14 +598,14 @@ request_complete (SIM_CPU *cpu, CACHE_QUEUE_ELEMENT *q)
}
/* Run the insn and data caches through the given number of cycles, taking
- note of load requests which are fullfilled as a result. */
+ note of load requests which are fulfilled as a result. */
static void
run_caches (SIM_CPU *cpu, int cycles)
{
FRV_CACHE* data_cache = CPU_DATA_CACHE (cpu);
FRV_CACHE* insn_cache = CPU_INSN_CACHE (cpu);
int i;
- /* For each cycle, run the caches, noting which requests have been fullfilled
+ /* For each cycle, run the caches, noting which requests have been fulfilled
and submitting new requests on their designated cycles. */
for (i = 0; i < cycles; ++i)
{
diff --git a/sim/frv/traps.c b/sim/frv/traps.c
index 9953145..006550d 100644
--- a/sim/frv/traps.c
+++ b/sim/frv/traps.c
@@ -780,7 +780,7 @@ frvbf_check_swap_address (SIM_CPU *current_cpu, SI address)
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
return;
- /* Adress must be aligned on a word boundary. */
+ /* Address must be aligned on a word boundary. */
if (address & 0x3)
frv_queue_data_access_exception_interrupt (current_cpu);
}