sim/bpf: desCGENization of the BPF simulator

The BPF port in binutils has been rewritten (commit
d218e7fedc74d67837d2134120917f4ac877454c) in order to not be longer
based on CGEN.  Please see that commit log for more information.

This patch updates the BPF simulator accordingly.  The new
implementation is much simpler and it is based on the new BPF opcodes.

Tested with target bpf-unknown-none with both 64-bit little-endian
host and 32-bit little-endian host.

Note that I have not tested in a big-endian host yet.  I will do so
once this lands upstream so I can use the GCC compiler farm.

1 files changed, 0 insertions, 81 deletions

diff --git a/sim/bpf/cpu.h b/sim/bpf/cpu.h
deleted file mode 100644
index d30da6c..0000000
--- a/sim/bpf/cpu.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* CPU family header for bpfbf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996-2023 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-   This file is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 3, or (at your option)
-   any later version.
-
-   It is distributed in the hope that it will be useful, but WITHOUT
-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-   License for more details.
-
-   You should have received a copy of the GNU General Public License along
-   with this program; if not, write to the Free Software Foundation, Inc.,
-   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-*/
-
-#ifndef CPU_BPFBF_H
-#define CPU_BPFBF_H
-
-/* Maximum number of instructions that are fetched at a time.
-   This is for LIW type instructions sets (e.g. m32r).  */
-#define MAX_LIW_INSNS 1
-
-/* Maximum number of instructions that can be executed in parallel.  */
-#define MAX_PARALLEL_INSNS 1
-
-/* The size of an "int" needed to hold an instruction word.
-   This is usually 32 bits, but some architectures needs 64 bits.  */
-typedef CGEN_INSN_LGUINT CGEN_INSN_WORD;
-
-#include "cgen-engine.h"
-
-/* CPU state information.  */
-typedef struct {
-  /* Hardware elements.  */
-  struct {
-  /* General Purpose Registers */
-  DI h_gpr[16];
-#define GET_H_GPR(a1) CPU (h_gpr)[a1]
-#define SET_H_GPR(a1, x) (CPU (h_gpr)[a1] = (x))
-  /* program counter */
-  UDI h_pc;
-#define GET_H_PC() CPU (h_pc)
-#define SET_H_PC(x) \
-do { \
-CPU (h_pc) = (x);\
-;} while (0)
-  } hardware;
-#define CPU_CGEN_HW(cpu) (& BPF_SIM_CPU (cpu)->cpu_data.hardware)
-} BPFBF_CPU_DATA;
-
-/* Cover fns for register access.  */
-DI bpfbf_h_gpr_get (SIM_CPU *, UINT);
-void bpfbf_h_gpr_set (SIM_CPU *, UINT, DI);
-UDI bpfbf_h_pc_get (SIM_CPU *);
-void bpfbf_h_pc_set (SIM_CPU *, UDI);
-
-/* These must be hand-written.  */
-extern CPUREG_FETCH_FN bpfbf_fetch_register;
-extern CPUREG_STORE_FN bpfbf_store_register;
-
-typedef struct {
-  int empty;
-} MODEL_BPF_DEF_DATA;
-
-/* Collection of various things for the trace handler to use.  */
-
-typedef struct trace_record {
-  IADDR pc;
-  /* FIXME:wip */
-} TRACE_RECORD;
-
-#endif /* CPU_BPFBF_H */