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authorAlexandre Oliva <aoliva@redhat.com>2000-06-22 20:03:32 +0000
committerAlexandre Oliva <aoliva@redhat.com>2000-06-22 20:03:32 +0000
commitee9a777240baf90e8c9714963fb791884162048c (patch)
tree4a9b6484785bf10bae7260fba4f939d2153928b6 /sim/arm
parent6d5be9157ea05325728d90e08ca13b3589f941a5 (diff)
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* armemu.c (MultiplyAdd64): Fix computation of flag N.
Diffstat (limited to 'sim/arm')
-rw-r--r--sim/arm/ChangeLog4
-rw-r--r--sim/arm/armemu.c7
2 files changed, 7 insertions, 4 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog
index a2329be..4780f0a 100644
--- a/sim/arm/ChangeLog
+++ b/sim/arm/ChangeLog
@@ -1,3 +1,7 @@
+2000-06-22 Alexandre Oliva <aoliva@cygnus.com>
+
+ * armemu.c (MultiplyAdd64): Fix computation of flag N.
+
2000-06-20 Alexandre Oliva <aoliva@cygnus.com>
* armemu.h (NEGBRANCH): Do not overwrite the two most significant
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
index acbcb75..426617d 100644
--- a/sim/arm/armemu.c
+++ b/sim/arm/armemu.c
@@ -3871,10 +3871,9 @@ MultiplyAdd64 (ARMul_State * state, ARMword instr, int msigned, int scc)
if (scc)
{
- if ((RdHi == 0) && (RdLo == 0))
- ARMul_NegZero (state, RdHi); /* zero value */
- else
- ARMul_NegZero (state, scc); /* non-zero value */
+ /* Ensure that both RdHi and RdLo are used to compute Z, but
+ don't let RdLo's sign bit make it to N. */
+ ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF));
}
return scount + 1; /* extra cycle for addition */