aboutsummaryrefslogtreecommitdiff
path: root/sim/arm/armemu.c
diff options
context:
space:
mode:
authornobody <>2002-01-07 20:43:47 +0000
committernobody <>2002-01-07 20:43:47 +0000
commit8bb26218880c35fa16f49c8741eb4fcba41b32ad (patch)
tree5a8047262747c4736eb97adf6c46ed12121252ff /sim/arm/armemu.c
parent494e8a93ef8840c384cd1fd48cc92d700ac61208 (diff)
downloadgdb-cygnus_cvs_20020108_pre.zip
gdb-cygnus_cvs_20020108_pre.tar.gz
gdb-cygnus_cvs_20020108_pre.tar.bz2
This commit was manufactured by cvs2svn to create tagcygnus_cvs_20020108_pre
'cygnus_cvs_20020108_pre'. Sprout from master 2002-01-07 20:43:46 UTC Jackie Smith Cashion <jsmith@redhat.com> '2002-01-07 Jackie Smith Cashion <jsmith@redhat.com>' Cherrypick from cygnus 2000-02-22 15:59:20 UTC Ian Lance Taylor <ian@airs.com> 'import libiberty from egcs': COPYING COPYING.LIB README bfd/PORTING bfd/TODO bfd/cf-m68klynx.c bfd/coff-svm68k.c bfd/coff-u68k.c bfd/configure.com bfd/cpu-d30v.c bfd/cpu-m10200.c bfd/cpu-tic30.c bfd/doc/doc.str bfd/doc/makefile.vms bfd/doc/proto.str bfd/elf64.c bfd/hosts/decstation.h bfd/hosts/delta68.h bfd/hosts/dpx2.h bfd/hosts/hp300bsd.h bfd/hosts/i386bsd.h bfd/hosts/i386linux.h bfd/hosts/i386mach3.h bfd/hosts/i386sco.h bfd/hosts/i860mach3.h bfd/hosts/m68kaux.h bfd/hosts/m68klinux.h bfd/hosts/m88kmach3.h bfd/hosts/mipsbsd.h bfd/hosts/mipsmach3.h bfd/hosts/news-mips.h bfd/hosts/news.h bfd/hosts/pc532mach.h bfd/hosts/riscos.h bfd/hosts/symmetry.h bfd/hosts/tahoe.h bfd/hosts/vaxbsd.h bfd/hosts/vaxult.h bfd/hosts/vaxult2.h bfd/makefile.vms bfd/mpw-config.in bfd/mpw-make.sed bfd/pe-mcore.c bfd/stamp-h.in binutils/configure.com binutils/dep-in.sed binutils/is-ranlib.c binutils/is-strip.c binutils/mac-binutils.r binutils/makefile.vms-in binutils/maybe-ranlib.c binutils/maybe-strip.c binutils/mpw-config.in binutils/mpw-make.sed binutils/not-ranlib.c binutils/not-strip.c binutils/po/Make-in binutils/ranlib.sh binutils/sanity.sh binutils/stamp-h.in binutils/sysroff.info binutils/testsuite/binutils-all/bintest.s binutils/testsuite/binutils-all/hppa/addendbug.s binutils/testsuite/config/hppa.sed binutils/winduni.h config/mh-a68bsd config/mh-aix386 config/mh-apollo68 config/mh-armpic config/mh-cxux config/mh-cygwin config/mh-decstation config/mh-delta88 config/mh-dgux config/mh-dgux386 config/mh-djgpp config/mh-elfalphapic config/mh-hp300 config/mh-hpux config/mh-hpux8 config/mh-interix config/mh-irix4 config/mh-irix5 config/mh-lynxos config/mh-lynxrs6k config/mh-m68kpic config/mh-mingw32 config/mh-ncr3000 config/mh-ncrsvr43 config/mh-necv4 config/mh-papic config/mh-ppcpic config/mh-riscos config/mh-sco config/mh-solaris config/mh-sun3 config/mh-sysv config/mh-sysv4 config/mh-sysv5 config/mh-vaxult2 config/mh-x86pic config/mpw-mh-mpw config/mpw/ChangeLog config/mpw/MoveIfChange config/mpw/README config/mpw/forward-include config/mpw/g-mpw-make.sed config/mpw/mpw-touch config/mpw/mpw-true config/mpw/null-command config/mpw/open-brace config/mpw/tr-7to8-src config/mpw/true config/mt-armpic config/mt-d30v config/mt-elfalphapic config/mt-linux config/mt-m68kpic config/mt-netware config/mt-ospace config/mt-papic config/mt-ppcpic config/mt-v810 config/mt-x86pic etc/Makefile.in etc/add-log.el etc/add-log.vi etc/configbuild.ein etc/configbuild.fig etc/configbuild.jin etc/configbuild.tin etc/configdev.ein etc/configdev.fig etc/configdev.jin etc/configdev.tin etc/configure etc/configure.in etc/configure.texi etc/make-stds.texi etc/standards.texi gas/README-vms gas/config-gas.com gas/config/e-mipsecoff.c gas/config/e-mipself.c gas/config/obj-generic.c gas/config/obj-multi.c gas/config/tc-generic.c gas/config/te-delt88.h gas/config/te-delta.h gas/config/te-dynix.h gas/config/te-epoc-pe.h gas/config/te-generic.h gas/config/te-linux.h gas/config/te-lnews.h gas/config/te-lynx.h gas/config/te-mach.h gas/config/te-macos.h gas/config/te-pe.h gas/config/te-riscix.h gas/config/te-svr4.h gas/config/vms-a-conf.h gas/doc/c-d30v.texi gas/doc/c-h8300.texi gas/doc/c-h8500.texi gas/doc/h8.texi gas/gdbinit.in gas/link.cmd gas/mac-as.r gas/makefile.vms gas/mpw-config.in gas/mpw-make.sed gas/po/Make-in gas/stamp-h.in gas/testsuite/gas/all/align.d gas/testsuite/gas/all/align.s gas/testsuite/gas/all/cofftag.s gas/testsuite/gas/all/comment.s gas/testsuite/gas/all/diff1.s gas/testsuite/gas/all/float.s gas/testsuite/gas/all/itbl gas/testsuite/gas/all/itbl.s gas/testsuite/gas/all/p1480.s gas/testsuite/gas/all/p2425.s gas/testsuite/gas/all/struct.d gas/testsuite/gas/all/struct.s gas/testsuite/gas/all/x930509.s gas/testsuite/gas/arc/alias.d gas/testsuite/gas/arc/alias.s gas/testsuite/gas/arc/branch.d gas/testsuite/gas/arc/branch.s gas/testsuite/gas/arc/flag.s gas/testsuite/gas/arc/insn3.d gas/testsuite/gas/arc/insn3.s gas/testsuite/gas/arc/math.d gas/testsuite/gas/arc/math.s gas/testsuite/gas/arc/sshift.d gas/testsuite/gas/arc/sshift.s gas/testsuite/gas/arm/arm3.s gas/testsuite/gas/arm/copro.s gas/testsuite/gas/arm/immed.s gas/testsuite/gas/arm/le-fpconst.d gas/testsuite/gas/arm/le-fpconst.s gas/testsuite/gas/d30v/align.d gas/testsuite/gas/d30v/align.s gas/testsuite/gas/d30v/array.d gas/testsuite/gas/d30v/array.s gas/testsuite/gas/d30v/bittest.d gas/testsuite/gas/d30v/bittest.s gas/testsuite/gas/d30v/d30.exp gas/testsuite/gas/d30v/guard-debug.d gas/testsuite/gas/d30v/guard-debug.s gas/testsuite/gas/d30v/guard.d gas/testsuite/gas/d30v/guard.s gas/testsuite/gas/d30v/inst.s gas/testsuite/gas/d30v/label-debug.d gas/testsuite/gas/d30v/label-debug.s gas/testsuite/gas/d30v/label.d gas/testsuite/gas/d30v/label.s gas/testsuite/gas/d30v/mul.d gas/testsuite/gas/d30v/mul.s gas/testsuite/gas/d30v/opt.d gas/testsuite/gas/d30v/opt.s gas/testsuite/gas/d30v/reloc.d gas/testsuite/gas/d30v/reloc.s gas/testsuite/gas/d30v/serial.l gas/testsuite/gas/d30v/serial.s gas/testsuite/gas/d30v/serial2.l gas/testsuite/gas/d30v/serial2.s gas/testsuite/gas/d30v/serial2O.l gas/testsuite/gas/d30v/serial2O.s gas/testsuite/gas/d30v/warn_oddreg.l gas/testsuite/gas/d30v/warn_oddreg.s gas/testsuite/gas/fr30/allinsn.d gas/testsuite/gas/fr30/allinsn.exp gas/testsuite/gas/fr30/allinsn.s gas/testsuite/gas/fr30/fr30.exp gas/testsuite/gas/h8300/addsub.s gas/testsuite/gas/h8300/addsubh.s gas/testsuite/gas/h8300/addsubs.s gas/testsuite/gas/h8300/bitops1.s gas/testsuite/gas/h8300/bitops1h.s gas/testsuite/gas/h8300/bitops1s.s gas/testsuite/gas/h8300/bitops2.s gas/testsuite/gas/h8300/bitops2h.s gas/testsuite/gas/h8300/bitops2s.s gas/testsuite/gas/h8300/bitops3.s gas/testsuite/gas/h8300/bitops3h.s gas/testsuite/gas/h8300/bitops3s.s gas/testsuite/gas/h8300/bitops4.s gas/testsuite/gas/h8300/bitops4h.s gas/testsuite/gas/h8300/bitops4s.s gas/testsuite/gas/h8300/cbranch.s gas/testsuite/gas/h8300/cbranchh.s gas/testsuite/gas/h8300/cbranchs.s gas/testsuite/gas/h8300/cmpsi2.s gas/testsuite/gas/h8300/compare.s gas/testsuite/gas/h8300/compareh.s gas/testsuite/gas/h8300/compares.s gas/testsuite/gas/h8300/decimal.s gas/testsuite/gas/h8300/decimalh.s gas/testsuite/gas/h8300/decimals.s gas/testsuite/gas/h8300/divmul.s gas/testsuite/gas/h8300/divmulh.s gas/testsuite/gas/h8300/divmuls.s gas/testsuite/gas/h8300/extendh.s gas/testsuite/gas/h8300/extends.s gas/testsuite/gas/h8300/incdec.s gas/testsuite/gas/h8300/incdech.s gas/testsuite/gas/h8300/incdecs.s gas/testsuite/gas/h8300/logical.s gas/testsuite/gas/h8300/logicalh.s gas/testsuite/gas/h8300/logicals.s gas/testsuite/gas/h8300/misc.s gas/testsuite/gas/h8300/misch.s gas/testsuite/gas/h8300/miscs.s gas/testsuite/gas/h8300/mov32bug.s gas/testsuite/gas/h8300/movb.s gas/testsuite/gas/h8300/movbh.s gas/testsuite/gas/h8300/movbs.s gas/testsuite/gas/h8300/movlh.s gas/testsuite/gas/h8300/movls.s gas/testsuite/gas/h8300/movw.s gas/testsuite/gas/h8300/movwh.s gas/testsuite/gas/h8300/movws.s gas/testsuite/gas/h8300/multiples.s gas/testsuite/gas/h8300/pushpop.s gas/testsuite/gas/h8300/pushpoph.s gas/testsuite/gas/h8300/pushpops.s gas/testsuite/gas/h8300/rotsh.s gas/testsuite/gas/h8300/rotshh.s gas/testsuite/gas/h8300/rotshs.s gas/testsuite/gas/hppa/README gas/testsuite/gas/hppa/basic/weird.s gas/testsuite/gas/hppa/parse/appbug.s gas/testsuite/gas/hppa/parse/nosubspace.s gas/testsuite/gas/hppa/parse/spacebug.s gas/testsuite/gas/hppa/parse/ssbug.s gas/testsuite/gas/hppa/reloc/reduce2.s gas/testsuite/gas/hppa/unsorted/align3.s gas/testsuite/gas/hppa/unsorted/align4.s gas/testsuite/gas/hppa/unsorted/globalbug.s gas/testsuite/gas/hppa/unsorted/ss_align.s gas/testsuite/gas/i386/inval.l gas/testsuite/gas/i386/inval.s gas/testsuite/gas/i386/opcode.s gas/testsuite/gas/ieee-fp/x930509a.s gas/testsuite/gas/m32r/allinsn.d gas/testsuite/gas/m32r/allinsn.exp gas/testsuite/gas/m32r/allinsn.s gas/testsuite/gas/m32r/fslot.d gas/testsuite/gas/m32r/fslot.s gas/testsuite/gas/m32r/high-1.d gas/testsuite/gas/m32r/high-1.s gas/testsuite/gas/m32r/m32r.exp gas/testsuite/gas/m32r/outofrange.s gas/testsuite/gas/m32r/relax-1.d gas/testsuite/gas/m32r/relax-1.s gas/testsuite/gas/m32r/uppercase.d gas/testsuite/gas/m32r/uppercase.s gas/testsuite/gas/m68k-coff/gas.exp gas/testsuite/gas/m68k-coff/p2389.s gas/testsuite/gas/m68k-coff/p2389a.s gas/testsuite/gas/m68k-coff/p2430.s gas/testsuite/gas/m68k-coff/p2430a.s gas/testsuite/gas/m68k-coff/t1.s gas/testsuite/gas/m68k/bitfield.d gas/testsuite/gas/m68k/bitfield.s gas/testsuite/gas/m68k/cas.d gas/testsuite/gas/m68k/cas.s gas/testsuite/gas/m68k/disperr.s gas/testsuite/gas/m68k/fmoveml.d gas/testsuite/gas/m68k/fmoveml.s gas/testsuite/gas/m68k/link.d gas/testsuite/gas/m68k/link.s gas/testsuite/gas/m68k/op68000.d gas/testsuite/gas/m68k/operands.d gas/testsuite/gas/m68k/operands.s gas/testsuite/gas/m68k/p2410.s gas/testsuite/gas/m68k/p2663.s gas/testsuite/gas/m68k/pic1.s gas/testsuite/gas/m68k/t2.d gas/testsuite/gas/m68k/t2.s gas/testsuite/gas/m88k/init.d gas/testsuite/gas/m88k/init.s gas/testsuite/gas/macros/err.s gas/testsuite/gas/macros/semi.d gas/testsuite/gas/macros/semi.s gas/testsuite/gas/macros/test1.d gas/testsuite/gas/macros/test1.s gas/testsuite/gas/mcore/allinsn.exp gas/testsuite/gas/mcore/allinsn.s gas/testsuite/gas/mips/abs.s gas/testsuite/gas/mips/add.s gas/testsuite/gas/mips/and.s gas/testsuite/gas/mips/break20.s gas/testsuite/gas/mips/delay.s gas/testsuite/gas/mips/div.s gas/testsuite/gas/mips/dli.s gas/testsuite/gas/mips/itbl gas/testsuite/gas/mips/itbl.s gas/testsuite/gas/mips/jal.s gas/testsuite/gas/mips/la-empic.s gas/testsuite/gas/mips/lb-pic.s gas/testsuite/gas/mips/lb.s gas/testsuite/gas/mips/ld-pic.s gas/testsuite/gas/mips/ld.s gas/testsuite/gas/mips/li.s gas/testsuite/gas/mips/lifloat.s gas/testsuite/gas/mips/lineno.s gas/testsuite/gas/mips/mips16.s gas/testsuite/gas/mips/mips4.s gas/testsuite/gas/mips/mul.s gas/testsuite/gas/mips/rol.s gas/testsuite/gas/mips/sb.s gas/testsuite/gas/mips/trap20.s gas/testsuite/gas/mips/trunc.s gas/testsuite/gas/mips/uld.s gas/testsuite/gas/mips/ulh-pic.s gas/testsuite/gas/mips/ulh.s gas/testsuite/gas/mips/ulw.s gas/testsuite/gas/mips/usd.s gas/testsuite/gas/mips/ush.s gas/testsuite/gas/mips/usw.s gas/testsuite/gas/mn10200/add.s gas/testsuite/gas/mn10200/basic.exp gas/testsuite/gas/mn10200/bcc.s gas/testsuite/gas/mn10200/bccx.s gas/testsuite/gas/mn10200/bit.s gas/testsuite/gas/mn10200/cmp.s gas/testsuite/gas/mn10200/ext.s gas/testsuite/gas/mn10200/logical.s gas/testsuite/gas/mn10200/mov1.s gas/testsuite/gas/mn10200/mov2.s gas/testsuite/gas/mn10200/mov3.s gas/testsuite/gas/mn10200/mov4.s gas/testsuite/gas/mn10200/movb.s gas/testsuite/gas/mn10200/movbu.s gas/testsuite/gas/mn10200/movx.s gas/testsuite/gas/mn10200/muldiv.s gas/testsuite/gas/mn10200/other.s gas/testsuite/gas/mn10200/shift.s gas/testsuite/gas/mn10200/sub.s gas/testsuite/gas/mn10300/add.s gas/testsuite/gas/mn10300/bcc.s gas/testsuite/gas/mn10300/bit.s gas/testsuite/gas/mn10300/cmp.s gas/testsuite/gas/mn10300/ext.s gas/testsuite/gas/mn10300/extend.s gas/testsuite/gas/mn10300/logical.s gas/testsuite/gas/mn10300/loop.s gas/testsuite/gas/mn10300/mov1.s gas/testsuite/gas/mn10300/mov2.s gas/testsuite/gas/mn10300/mov3.s gas/testsuite/gas/mn10300/mov4.s gas/testsuite/gas/mn10300/movbu.s gas/testsuite/gas/mn10300/movhu.s gas/testsuite/gas/mn10300/movm.s gas/testsuite/gas/mn10300/muldiv.s gas/testsuite/gas/mn10300/other.s gas/testsuite/gas/mn10300/shift.s gas/testsuite/gas/mn10300/sub.s gas/testsuite/gas/mn10300/udf.s gas/testsuite/gas/mri/char.d gas/testsuite/gas/mri/char.s gas/testsuite/gas/mri/comment.d gas/testsuite/gas/mri/comment.s gas/testsuite/gas/mri/common.d gas/testsuite/gas/mri/common.s gas/testsuite/gas/mri/constants.d gas/testsuite/gas/mri/constants.s gas/testsuite/gas/mri/empty.s gas/testsuite/gas/mri/equ.d gas/testsuite/gas/mri/equ.s gas/testsuite/gas/mri/expr.d gas/testsuite/gas/mri/expr.s gas/testsuite/gas/mri/float.s gas/testsuite/gas/mri/for.s gas/testsuite/gas/mri/if.s gas/testsuite/gas/mri/immconst.d gas/testsuite/gas/mri/label.d gas/testsuite/gas/mri/label.s gas/testsuite/gas/mri/moveml.d gas/testsuite/gas/mri/moveml.s gas/testsuite/gas/mri/repeat.s gas/testsuite/gas/mri/semi.d gas/testsuite/gas/mri/semi.s gas/testsuite/gas/mri/while.s gas/testsuite/gas/ppc/astest.d gas/testsuite/gas/ppc/astest.s gas/testsuite/gas/ppc/astest2.d gas/testsuite/gas/ppc/astest2.s gas/testsuite/gas/ppc/simpshft.d gas/testsuite/gas/sh/fp.s gas/testsuite/gas/sparc-solaris/addend.exp gas/testsuite/gas/sparc-solaris/addend.s gas/testsuite/gas/sparc-solaris/gas.exp gas/testsuite/gas/sparc-solaris/sol-cc.s gas/testsuite/gas/sparc-solaris/sol-gcc.s gas/testsuite/gas/sparc/asi.d gas/testsuite/gas/sparc/asi.s gas/testsuite/gas/sparc/membar.d gas/testsuite/gas/sparc/membar.s gas/testsuite/gas/sparc/mism-1.s gas/testsuite/gas/sparc/mismatch.exp gas/testsuite/gas/sparc/prefetch.s gas/testsuite/gas/sparc/rdpr.s gas/testsuite/gas/sparc/reloc64.s gas/testsuite/gas/sparc/splet-2.d gas/testsuite/gas/sparc/splet-2.s gas/testsuite/gas/sparc/splet.d gas/testsuite/gas/sparc/splet.s gas/testsuite/gas/sparc/synth.d gas/testsuite/gas/sparc/synth.s gas/testsuite/gas/sparc/wrpr.s gas/testsuite/gas/sun4/addend.d gas/testsuite/gas/sun4/addend.exp gas/testsuite/gas/sun4/addend.s gas/testsuite/gas/template gas/testsuite/gas/tic80/add.d gas/testsuite/gas/tic80/add.lst gas/testsuite/gas/tic80/add.s gas/testsuite/gas/tic80/align.d gas/testsuite/gas/tic80/align.lst gas/testsuite/gas/tic80/align.s gas/testsuite/gas/tic80/bitnum.d gas/testsuite/gas/tic80/bitnum.lst gas/testsuite/gas/tic80/bitnum.s gas/testsuite/gas/tic80/ccode.d gas/testsuite/gas/tic80/ccode.lst gas/testsuite/gas/tic80/ccode.s gas/testsuite/gas/tic80/cregops.d gas/testsuite/gas/tic80/cregops.lst gas/testsuite/gas/tic80/cregops.s gas/testsuite/gas/tic80/endmask.d gas/testsuite/gas/tic80/endmask.lst gas/testsuite/gas/tic80/endmask.s gas/testsuite/gas/tic80/float.d gas/testsuite/gas/tic80/float.lst gas/testsuite/gas/tic80/float.s gas/testsuite/gas/tic80/regops.d gas/testsuite/gas/tic80/regops.lst gas/testsuite/gas/tic80/regops.s gas/testsuite/gas/tic80/regops2.d gas/testsuite/gas/tic80/regops2.lst gas/testsuite/gas/tic80/regops2.s gas/testsuite/gas/tic80/regops3.d gas/testsuite/gas/tic80/regops3.lst gas/testsuite/gas/tic80/regops3.s gas/testsuite/gas/tic80/regops4.d gas/testsuite/gas/tic80/regops4.lst gas/testsuite/gas/tic80/regops4.s gas/testsuite/gas/tic80/relocs1.c gas/testsuite/gas/tic80/relocs1.d gas/testsuite/gas/tic80/relocs1.lst gas/testsuite/gas/tic80/relocs1.s gas/testsuite/gas/tic80/relocs1b.d gas/testsuite/gas/tic80/relocs2.c gas/testsuite/gas/tic80/relocs2.d gas/testsuite/gas/tic80/relocs2.lst gas/testsuite/gas/tic80/relocs2.s gas/testsuite/gas/tic80/relocs2b.d gas/testsuite/gas/tic80/tic80.exp gas/testsuite/gas/v850/arith.s gas/testsuite/gas/v850/basic.exp gas/testsuite/gas/v850/bit.s gas/testsuite/gas/v850/branch.s gas/testsuite/gas/v850/compare.s gas/testsuite/gas/v850/fepsw.s gas/testsuite/gas/v850/hilo.s gas/testsuite/gas/v850/hilo2.s gas/testsuite/gas/v850/jumps.s gas/testsuite/gas/v850/logical.s gas/testsuite/gas/v850/mem.s gas/testsuite/gas/v850/misc.s gas/testsuite/gas/v850/move.s gas/testsuite/gas/v850/range.s gas/testsuite/gas/v850/reloc.s gas/testsuite/gas/vax/quad.s gas/testsuite/gas/vtable/entry0.d gas/testsuite/gas/vtable/entry1.d gas/testsuite/gas/vtable/inherit0.d gas/testsuite/gas/vtable/inherit1.l gas/testsuite/gasp/INC1.H gas/testsuite/gasp/INC2.H gas/testsuite/gasp/assign.asm gas/testsuite/gasp/assign.err gas/testsuite/gasp/assign.out gas/testsuite/gasp/condass.asm gas/testsuite/gasp/condass.err gas/testsuite/gasp/condass.out gas/testsuite/gasp/crash.asm gas/testsuite/gasp/crash.err gas/testsuite/gasp/crash.out gas/testsuite/gasp/crash1.asm gas/testsuite/gasp/crash1.err gas/testsuite/gasp/crash1.out gas/testsuite/gasp/crash2.asm gas/testsuite/gasp/crash2.err gas/testsuite/gasp/crash2.out gas/testsuite/gasp/data.asm gas/testsuite/gasp/data.err gas/testsuite/gasp/data.out gas/testsuite/gasp/exp.asm gas/testsuite/gasp/exp.err gas/testsuite/gasp/exp.out gas/testsuite/gasp/gasp.exp gas/testsuite/gasp/include.asm gas/testsuite/gasp/include.err gas/testsuite/gasp/include.out gas/testsuite/gasp/listing.asm gas/testsuite/gasp/listing.err gas/testsuite/gasp/listing.out gas/testsuite/gasp/macro.asm gas/testsuite/gasp/macro.err gas/testsuite/gasp/mdouble.asm gas/testsuite/gasp/mdouble.err gas/testsuite/gasp/mri/embed.asm gas/testsuite/gasp/mri/embed.out gas/testsuite/gasp/mri/exists.asm gas/testsuite/gasp/mri/exists.out gas/testsuite/gasp/mri/irp.asm gas/testsuite/gasp/mri/irp.out gas/testsuite/gasp/mri/irpc.asm gas/testsuite/gasp/mri/irpc.out gas/testsuite/gasp/mri/macro.asm gas/testsuite/gasp/mri/macro.out gas/testsuite/gasp/mri/narg.asm gas/testsuite/gasp/mri/narg.out gas/testsuite/gasp/mri/rept.asm gas/testsuite/gasp/mri/rept.out gas/testsuite/gasp/pl1.asm gas/testsuite/gasp/pl1.err gas/testsuite/gasp/pl1.out gas/testsuite/gasp/pl2.asm gas/testsuite/gasp/pl2.err gas/testsuite/gasp/pl2.out gas/testsuite/gasp/pl3.asm gas/testsuite/gasp/pl3.err gas/testsuite/gasp/pl3.out gas/testsuite/gasp/pl4.asm gas/testsuite/gasp/pl4.err gas/testsuite/gasp/pl4.out gas/testsuite/gasp/pl5.asm gas/testsuite/gasp/pl5.err gas/testsuite/gasp/pl5.out gas/testsuite/gasp/pl6.asm gas/testsuite/gasp/pl6.err gas/testsuite/gasp/pl6.out gas/testsuite/gasp/pl7.asm gas/testsuite/gasp/pl7.err gas/testsuite/gasp/pl7.out gas/testsuite/gasp/pl8.asm gas/testsuite/gasp/pl8.err gas/testsuite/gasp/pl8.out gas/testsuite/gasp/pr7583.asm gas/testsuite/gasp/pr7583.err gas/testsuite/gasp/pr7583.out gas/testsuite/gasp/reg.asm gas/testsuite/gasp/reg.err gas/testsuite/gasp/reg.out gas/testsuite/gasp/rep.asm gas/testsuite/gasp/rep.err gas/testsuite/gasp/rep.out gas/testsuite/gasp/repeat.asm gas/testsuite/gasp/repeat.err gas/testsuite/gasp/repeat.out gas/testsuite/gasp/reperr.asm gas/testsuite/gasp/reperr.err gas/testsuite/gasp/reperr.out gas/testsuite/gasp/reperr1.asm gas/testsuite/gasp/reperr1.err gas/testsuite/gasp/reperr1.out gas/testsuite/gasp/reperr2.asm gas/testsuite/gasp/reperr2.err gas/testsuite/gasp/reperr2.out gas/testsuite/gasp/reperr3.asm gas/testsuite/gasp/reperr3.err gas/testsuite/gasp/reperr3.out gas/testsuite/gasp/sdata.asm gas/testsuite/gasp/sdata.err gas/testsuite/gasp/sdata.out gas/testsuite/gasp/sfunc.asm gas/testsuite/gasp/sfunc.err gas/testsuite/gasp/sfunc.out gas/testsuite/gasp/t1.asm gas/testsuite/gasp/t1.err gas/testsuite/gasp/t1.out gas/testsuite/gasp/t2.asm gas/testsuite/gasp/t2.err gas/testsuite/gasp/t2.out gas/testsuite/gasp/t3.asm gas/testsuite/gasp/t3.err gas/testsuite/gasp/t3.out gas/testsuite/gasp/while.asm gas/testsuite/gasp/while.err gas/testsuite/gasp/while.out gas/testsuite/lib/doboth gas/testsuite/lib/doobjcmp gas/testsuite/lib/dostriptest gas/testsuite/lib/dotest gas/testsuite/lib/dounsreloc gas/testsuite/lib/dounssym gas/testsuite/lib/gas-dg.exp gas/testsuite/lib/run gas/vmsconf.sh gprof/.gdbinit gprof/TEST gprof/TODO gprof/bsd_callg_bl.m gprof/cg_arcs.h gprof/cg_dfn.h gprof/flat_bl.m gprof/fsf_callg_bl.m gprof/gen-c-prog.awk gprof/po/Make-in gprof/stamp-h.in gprof/utils.h include/aout/hp.h include/aout/hppa.h include/callback.h include/coff/sym.h include/coff/symconst.h include/fopen-bin.h include/fopen-same.h include/fopen-vms.h include/gdbm.h include/mpw/ChangeLog include/mpw/README include/mpw/dir.h include/mpw/dirent.h include/mpw/fcntl.h include/mpw/grp.h include/mpw/mpw.h include/mpw/pwd.h include/mpw/stat.h include/mpw/sys/file.h include/mpw/sys/param.h include/mpw/sys/resource.h include/mpw/sys/stat.h include/mpw/sys/time.h include/mpw/sys/types.h include/mpw/utime.h include/mpw/varargs.h include/nlm/ppc-ext.h include/opcode/mn10200.h include/opcode/tahoe.h include/opcode/tic30.h include/regs/ChangeLog install-sh ld/TODO ld/emulparams/README ld/emulparams/a29k.sh ld/emulparams/alpha.sh ld/emulparams/arcelf.sh ld/emulparams/armaoutb.sh ld/emulparams/armaoutl.sh ld/emulparams/armcoff.sh ld/emulparams/coff_sparc.sh ld/emulparams/d30v_e.sh ld/emulparams/d30v_o.sh ld/emulparams/d30velf.sh ld/emulparams/delta68.sh ld/emulparams/ebmon29k.sh ld/emulparams/gld960.sh ld/emulparams/gld960coff.sh ld/emulparams/h8300.sh ld/emulparams/h8300h.sh ld/emulparams/h8300s.sh ld/emulparams/h8500.sh ld/emulparams/h8500b.sh ld/emulparams/h8500c.sh ld/emulparams/h8500m.sh ld/emulparams/h8500s.sh ld/emulparams/hp300bsd.sh ld/emulparams/hp3hpux.sh ld/emulparams/i386aout.sh ld/emulparams/i386beos.sh ld/emulparams/i386bsd.sh ld/emulparams/i386coff.sh ld/emulparams/i386go32.sh ld/emulparams/i386linux.sh ld/emulparams/i386lynx.sh ld/emulparams/i386mach.sh ld/emulparams/i386msdos.sh ld/emulparams/i386nbsd.sh ld/emulparams/lnk960.sh ld/emulparams/m68k4knbsd.sh ld/emulparams/m68kaout.sh ld/emulparams/m68kaux.sh ld/emulparams/m68klinux.sh ld/emulparams/m68klynx.sh ld/emulparams/m68knbsd.sh ld/emulparams/m68kpsos.sh ld/emulparams/m88kbcs.sh ld/emulparams/mipsbig.sh ld/emulparams/mipsbsd.sh ld/emulparams/mipsidt.sh ld/emulparams/mipsidtl.sh ld/emulparams/mipslit.sh ld/emulparams/mipslnews.sh ld/emulparams/news.sh ld/emulparams/ns32knbsd.sh ld/emulparams/pc532macha.sh ld/emulparams/ppcnw.sh ld/emulparams/riscix.sh ld/emulparams/sa29200.sh ld/emulparams/sparcaout.sh ld/emulparams/sparclinux.sh ld/emulparams/sparclynx.sh ld/emulparams/sparcnbsd.sh ld/emulparams/st2000.sh ld/emulparams/sun3.sh ld/emulparams/sun4.sh ld/emulparams/tic30aout.sh ld/emulparams/tic30coff.sh ld/emulparams/tic80coff.sh ld/emulparams/v850.sh ld/emulparams/vanilla.sh ld/emulparams/vax.sh ld/emulparams/vsta.sh ld/emulparams/w65.sh ld/emulparams/z8001.sh ld/emulparams/z8002.sh ld/emultempl/README ld/h8-doc.texi ld/ldwrite.h ld/mac-ld.r ld/mpw-config.in ld/mpw-make.sed ld/po/Make-in ld/scripttempl/README ld/scripttempl/a29k.sc ld/scripttempl/alpha.sc ld/scripttempl/aout.sc ld/scripttempl/delta68.sc ld/scripttempl/ebmon29k.sc ld/scripttempl/hppaelf.sc ld/scripttempl/i386coff.sc ld/scripttempl/i386lynx.sc ld/scripttempl/i386msdos.sc ld/scripttempl/i960.sc ld/scripttempl/m68kaux.sc ld/scripttempl/m68kcoff.sc ld/scripttempl/m68klynx.sc ld/scripttempl/m88kbcs.sc ld/scripttempl/mips.sc ld/scripttempl/mipsbsd.sc ld/scripttempl/ppcpe.sc ld/scripttempl/psos.sc ld/scripttempl/riscix.sc ld/scripttempl/sa29200.sc ld/scripttempl/sh.sc ld/scripttempl/sparccoff.sc ld/scripttempl/sparclynx.sc ld/scripttempl/st2000.sc ld/scripttempl/tic30aout.sc ld/scripttempl/tic30coff.sc ld/scripttempl/tic80coff.sc ld/scripttempl/vanilla.sc ld/stamp-h.in ld/testsuite/ld-cdtest/cdtest-bar.cc ld/testsuite/ld-cdtest/cdtest-foo.h ld/testsuite/ld-cdtest/cdtest.dat ld/testsuite/ld-checks/script ld/testsuite/ld-elfvers/vers1.dsym ld/testsuite/ld-elfvers/vers1.map ld/testsuite/ld-elfvers/vers1.sym ld/testsuite/ld-elfvers/vers13.asym ld/testsuite/ld-elfvers/vers15.dsym ld/testsuite/ld-elfvers/vers15.sym ld/testsuite/ld-elfvers/vers16.c ld/testsuite/ld-elfvers/vers16.dsym ld/testsuite/ld-elfvers/vers16.map ld/testsuite/ld-elfvers/vers16a.c ld/testsuite/ld-elfvers/vers16a.dsym ld/testsuite/ld-elfvers/vers2.dsym ld/testsuite/ld-elfvers/vers2.map ld/testsuite/ld-elfvers/vers3.dsym ld/testsuite/ld-elfvers/vers4.sym ld/testsuite/ld-elfvers/vers4a.dsym ld/testsuite/ld-elfvers/vers4a.sym ld/testsuite/ld-elfvers/vers5.c ld/testsuite/ld-elfvers/vers6.dsym ld/testsuite/ld-elfvers/vers6.sym ld/testsuite/ld-elfvers/vers7.map ld/testsuite/ld-elfvers/vers7a.c ld/testsuite/ld-elfvers/vers7a.dsym ld/testsuite/ld-elfvers/vers7a.sym ld/testsuite/ld-elfvers/vers8.c ld/testsuite/ld-elfvers/vers8.map ld/testsuite/ld-elfvers/vers9.dsym ld/testsuite/ld-elfvers/vers9.sym ld/testsuite/ld-empic/relax.t ld/testsuite/ld-empic/relax1.c ld/testsuite/ld-empic/relax2.c ld/testsuite/ld-empic/relax3.c ld/testsuite/ld-empic/relax4.c ld/testsuite/ld-empic/run.c ld/testsuite/ld-empic/runtest1.c ld/testsuite/ld-empic/runtest2.c ld/testsuite/ld-empic/runtesti.s ld/testsuite/ld-scripts/cross1.c ld/testsuite/ld-scripts/cross2.c ld/testsuite/ld-scripts/cross3.c ld/testsuite/ld-scripts/defined.s ld/testsuite/ld-scripts/defined.t ld/testsuite/ld-scripts/phdrs.s ld/testsuite/ld-scripts/script.s ld/testsuite/ld-scripts/script.t ld/testsuite/ld-scripts/scriptm.t ld/testsuite/ld-scripts/sizeof.s ld/testsuite/ld-scripts/sizeof.t ld/testsuite/ld-scripts/weak.t ld/testsuite/ld-scripts/weak1.s ld/testsuite/ld-scripts/weak2.s ld/testsuite/ld-selective/1.c ld/testsuite/ld-selective/2.c ld/testsuite/ld-sh/sh1.s ld/testsuite/ld-sh/sh2.c ld/testsuite/ld-sh/start.s ld/testsuite/ld-shared/elf-offset.ld ld/testsuite/ld-shared/sh2.c ld/testsuite/ld-shared/shared.dat ld/testsuite/ld-shared/sun4.dat ld/testsuite/ld-shared/xcoff.dat ld/testsuite/ld-srec/sr1.c ld/testsuite/ld-srec/sr2.c ld/testsuite/ld-undefined/undefined.c ld/testsuite/ld-versados/t1-1.ro ld/testsuite/ld-versados/t1-2.ro ld/testsuite/ld-versados/t1.ld ld/testsuite/ld-versados/t1.ook ld/testsuite/ld-versados/t2-1.ro ld/testsuite/ld-versados/t2-2.ro ld/testsuite/ld-versados/t2-3.ro ld/testsuite/ld-versados/t2.ld ld/testsuite/ld-versados/t2.ook libiberty/README libiberty/config.h-vms libiberty/config/mh-aix libiberty/config/mh-cxux7 libiberty/config/mh-fbsd21 libiberty/config/mh-windows libiberty/copysign.c libiberty/makefile.vms libiberty/mpw-config.in libiberty/mpw-make.sed libiberty/mpw.c libiberty/msdos.c libiberty/testsuite/Makefile.in libiberty/vfprintf.c libiberty/vmsbuild.com libiberty/vsprintf.c makefile.vms missing mkinstalldirs move-if-change mpw-README mpw-build.in mpw-config.in mpw-configure mpw-install opcodes/dep-in.sed opcodes/makefile.vms opcodes/mpw-config.in opcodes/mpw-make.sed opcodes/po/Make-in opcodes/stamp-h.in setup.com ylwrap Cherrypick from FSF 2000-07-09 16:21:23 UTC Elena Zannoni <ezannoni@kwikemart.cygnus.com> 'Import of readline 4.1': readline/USAGE readline/doc/rluserman.texinfo readline/examples/excallback.c readline/examples/rlfe.c readline/rlprivate.h readline/rlshell.h readline/xmalloc.h Delete: gdb/windows-nat.c sim/ChangeLog sim/MAINTAINERS sim/Makefile.in sim/README-HACKING sim/arm/COPYING sim/arm/ChangeLog sim/arm/Makefile.in sim/arm/README.Cygnus sim/arm/acconfig.h sim/arm/armcopro.c sim/arm/armdefs.h sim/arm/armemu.c sim/arm/armemu.h sim/arm/armfpe.h sim/arm/arminit.c sim/arm/armopts.h sim/arm/armos.c sim/arm/armos.h sim/arm/armrdi.c sim/arm/armsupp.c sim/arm/armvirt.c sim/arm/bag.c sim/arm/bag.h sim/arm/communicate.c sim/arm/communicate.h sim/arm/config.in sim/arm/configure sim/arm/configure.in sim/arm/dbg_conf.h sim/arm/dbg_cp.h sim/arm/dbg_hif.h sim/arm/dbg_rdi.h sim/arm/gdbhost.c sim/arm/gdbhost.h sim/arm/kid.c sim/arm/main.c sim/arm/parent.c sim/arm/tconfig.in sim/arm/thumbemu.c sim/arm/wrapper.c sim/common/ChangeLog sim/common/Make-common.in sim/common/Makefile.in sim/common/acconfig.h sim/common/aclocal.m4 sim/common/callback.c sim/common/cgen-accfp.c sim/common/cgen-cpu.h sim/common/cgen-defs.h sim/common/cgen-engine.h sim/common/cgen-fpu.c sim/common/cgen-fpu.h sim/common/cgen-mem.h sim/common/cgen-ops.h sim/common/cgen-par.c sim/common/cgen-par.h sim/common/cgen-run.c sim/common/cgen-scache.c sim/common/cgen-scache.h sim/common/cgen-sim.h sim/common/cgen-trace.c sim/common/cgen-trace.h sim/common/cgen-types.h sim/common/cgen-utils.c sim/common/cgen.sh sim/common/config.in sim/common/configure sim/common/configure.in sim/common/dv-core.c sim/common/dv-glue.c sim/common/dv-pal.c sim/common/dv-sockser.c sim/common/dv-sockser.h sim/common/gdbinit.in sim/common/genmloop.sh sim/common/gennltvals.sh sim/common/gentmap.c sim/common/gentvals.sh sim/common/hw-alloc.c sim/common/hw-alloc.h sim/common/hw-base.c sim/common/hw-base.h sim/common/hw-device.c sim/common/hw-device.h sim/common/hw-events.c sim/common/hw-events.h sim/common/hw-handles.c sim/common/hw-handles.h sim/common/hw-instances.c sim/common/hw-instances.h sim/common/hw-main.h sim/common/hw-ports.c sim/common/hw-ports.h sim/common/hw-properties.c sim/common/hw-properties.h sim/common/hw-tree.c sim/common/hw-tree.h sim/common/nltvals.def sim/common/nrun.c sim/common/run.1 sim/common/run.c sim/common/sim-abort.c sim/common/sim-alu.h sim/common/sim-arange.c sim/common/sim-arange.h sim/common/sim-assert.h sim/common/sim-base.h sim/common/sim-basics.h sim/common/sim-bits.c sim/common/sim-bits.h sim/common/sim-break.c sim/common/sim-break.h sim/common/sim-config.c sim/common/sim-config.h sim/common/sim-core.c sim/common/sim-core.h sim/common/sim-cpu.c sim/common/sim-cpu.h sim/common/sim-endian.c sim/common/sim-endian.h sim/common/sim-engine.c sim/common/sim-engine.h sim/common/sim-events.c sim/common/sim-events.h sim/common/sim-fpu.c sim/common/sim-fpu.h sim/common/sim-hload.c sim/common/sim-hrw.c sim/common/sim-hw.c sim/common/sim-hw.h sim/common/sim-info.c sim/common/sim-inline.c sim/common/sim-inline.h sim/common/sim-io.c sim/common/sim-io.h sim/common/sim-load.c sim/common/sim-memopt.c sim/common/sim-memopt.h sim/common/sim-model.c sim/common/sim-model.h sim/common/sim-module.c sim/common/sim-module.h sim/common/sim-n-bits.h sim/common/sim-n-core.h sim/common/sim-n-endian.h sim/common/sim-options.c sim/common/sim-options.h sim/common/sim-profile.c sim/common/sim-profile.h sim/common/sim-reason.c sim/common/sim-reg.c sim/common/sim-resume.c sim/common/sim-run.c sim/common/sim-signal.c sim/common/sim-signal.h sim/common/sim-stop.c sim/common/sim-trace.c sim/common/sim-trace.h sim/common/sim-types.h sim/common/sim-utils.c sim/common/sim-utils.h sim/common/sim-watch.c sim/common/sim-watch.h sim/common/syscall.c sim/common/tconfig.in sim/configure sim/configure.in sim/d10v/ChangeLog sim/d10v/Makefile.in sim/d10v/acconfig.h sim/d10v/config.in sim/d10v/configure sim/d10v/configure.in sim/d10v/d10v_sim.h sim/d10v/endian.c sim/d10v/gencode.c sim/d10v/interp.c sim/d10v/simops.c sim/d30v/ChangeLog sim/d30v/Makefile.in sim/d30v/acconfig.h sim/d30v/alu.h sim/d30v/config.in sim/d30v/configure sim/d30v/configure.in sim/d30v/cpu.c sim/d30v/cpu.h sim/d30v/d30v-insns sim/d30v/dc-short sim/d30v/engine.c sim/d30v/ic-d30v sim/d30v/sim-calls.c sim/d30v/sim-main.h sim/d30v/tconfig.in sim/erc32/ChangeLog sim/erc32/Makefile.in sim/erc32/NEWS sim/erc32/README.erc32 sim/erc32/README.gdb sim/erc32/README.sis sim/erc32/acconfig.h sim/erc32/config.in sim/erc32/configure sim/erc32/configure.in sim/erc32/end.c sim/erc32/erc32.c sim/erc32/exec.c sim/erc32/float.c sim/erc32/func.c sim/erc32/help.c sim/erc32/interf.c sim/erc32/sis.c sim/erc32/sis.h sim/erc32/startsim sim/fr30/ChangeLog sim/fr30/Makefile.in sim/fr30/README sim/fr30/TODO sim/fr30/arch.c sim/fr30/arch.h sim/fr30/config.in sim/fr30/configure sim/fr30/configure.in sim/fr30/cpu.c sim/fr30/cpu.h sim/fr30/cpuall.h sim/fr30/decode.c sim/fr30/decode.h sim/fr30/devices.c sim/fr30/fr30-sim.h sim/fr30/fr30.c sim/fr30/mloop.in sim/fr30/model.c sim/fr30/sem-switch.c sim/fr30/sem.c sim/fr30/sim-if.c sim/fr30/sim-main.h sim/fr30/tconfig.in sim/fr30/traps.c sim/h8300/ChangeLog sim/h8300/Makefile.in sim/h8300/acconfig.h sim/h8300/compile.c sim/h8300/config.in sim/h8300/configure sim/h8300/configure.in sim/h8300/inst.h sim/h8300/tconfig.in sim/h8300/writecode.c sim/h8500/ChangeLog sim/h8500/Makefile.in sim/h8500/acconfig.h sim/h8500/compile.c sim/h8500/config.in sim/h8500/configure sim/h8500/configure.in sim/h8500/inst.h sim/h8500/tconfig.in sim/i960/ChangeLog sim/i960/Makefile.in sim/i960/README sim/i960/TODO sim/i960/acconfig.h sim/i960/arch.c sim/i960/arch.h sim/i960/config.in sim/i960/configure sim/i960/configure.in sim/i960/cpu.c sim/i960/cpu.h sim/i960/cpuall.h sim/i960/decode.c sim/i960/decode.h sim/i960/devices.c sim/i960/i960-desc.c sim/i960/i960-desc.h sim/i960/i960-opc.h sim/i960/i960-sim.h sim/i960/i960.c sim/i960/mloop.in sim/i960/model.c sim/i960/sem-switch.c sim/i960/sem.c sim/i960/sim-if.c sim/i960/sim-main.h sim/i960/tconfig.in sim/i960/traps.c sim/igen/ChangeLog sim/igen/Makefile.in sim/igen/acconfig.h sim/igen/config.in sim/igen/configure sim/igen/configure.in sim/igen/filter.c sim/igen/filter.h sim/igen/filter_host.c sim/igen/filter_host.h sim/igen/gen-engine.c sim/igen/gen-engine.h sim/igen/gen-icache.c sim/igen/gen-icache.h sim/igen/gen-idecode.c sim/igen/gen-idecode.h sim/igen/gen-itable.c sim/igen/gen-itable.h sim/igen/gen-model.c sim/igen/gen-model.h sim/igen/gen-semantics.c sim/igen/gen-semantics.h sim/igen/gen-support.c sim/igen/gen-support.h sim/igen/gen.c sim/igen/gen.h sim/igen/igen.c sim/igen/igen.h sim/igen/ld-cache.c sim/igen/ld-cache.h sim/igen/ld-decode.c sim/igen/ld-decode.h sim/igen/ld-insn.c sim/igen/ld-insn.h sim/igen/lf.c sim/igen/lf.h sim/igen/misc.c sim/igen/misc.h sim/igen/table.c sim/igen/table.h sim/m32r/ChangeLog sim/m32r/Makefile.in sim/m32r/README sim/m32r/TODO sim/m32r/acconfig.h sim/m32r/arch.c sim/m32r/arch.h sim/m32r/config.in sim/m32r/configure sim/m32r/configure.in sim/m32r/cpu.c sim/m32r/cpu.h sim/m32r/cpuall.h sim/m32r/cpux.c sim/m32r/cpux.h sim/m32r/decode.c sim/m32r/decode.h sim/m32r/decodex.c sim/m32r/decodex.h sim/m32r/devices.c sim/m32r/m32r-sim.h sim/m32r/m32r.c sim/m32r/m32rx.c sim/m32r/mloop.in sim/m32r/mloopx.in sim/m32r/model.c sim/m32r/modelx.c sim/m32r/sem-switch.c sim/m32r/sem.c sim/m32r/semx-switch.c sim/m32r/sim-if.c sim/m32r/sim-main.h sim/m32r/tconfig.in sim/m32r/traps.c sim/m68hc11/ChangeLog sim/m68hc11/Makefile.in sim/m68hc11/config.in sim/m68hc11/configure sim/m68hc11/configure.in sim/m68hc11/dv-m68hc11.c sim/m68hc11/dv-m68hc11eepr.c sim/m68hc11/dv-m68hc11sio.c sim/m68hc11/dv-m68hc11spi.c sim/m68hc11/dv-m68hc11tim.c sim/m68hc11/dv-nvram.c sim/m68hc11/emulos.c sim/m68hc11/gencode.c sim/m68hc11/interp.c sim/m68hc11/interrupts.c sim/m68hc11/interrupts.h sim/m68hc11/m68hc11_sim.c sim/m68hc11/sim-main.h sim/mcore/ChangeLog sim/mcore/Makefile.in sim/mcore/config.in sim/mcore/configure sim/mcore/configure.in sim/mcore/interp.c sim/mcore/sysdep.h sim/mips/ChangeLog sim/mips/Makefile.in sim/mips/acconfig.h sim/mips/config.in sim/mips/configure sim/mips/configure.in sim/mips/dv-tx3904cpu.c sim/mips/dv-tx3904irc.c sim/mips/dv-tx3904sio.c sim/mips/dv-tx3904tmr.c sim/mips/interp.c sim/mips/m16.dc sim/mips/m16.igen sim/mips/m16run.c sim/mips/mips.dc sim/mips/mips.igen sim/mips/sim-main.c sim/mips/sim-main.h sim/mips/tconfig.in sim/mips/tx.igen sim/mips/vr.igen sim/mn10200/ChangeLog sim/mn10200/Makefile.in sim/mn10200/acconfig.h sim/mn10200/config.in sim/mn10200/configure sim/mn10200/configure.in sim/mn10200/gencode.c sim/mn10200/interp.c sim/mn10200/mn10200_sim.h sim/mn10200/simops.c sim/mn10300/ChangeLog sim/mn10300/Makefile.in sim/mn10300/acconfig.h sim/mn10300/am33.igen sim/mn10300/config.in sim/mn10300/configure sim/mn10300/configure.in sim/mn10300/dv-mn103cpu.c sim/mn10300/dv-mn103int.c sim/mn10300/dv-mn103iop.c sim/mn10300/dv-mn103ser.c sim/mn10300/dv-mn103tim.c sim/mn10300/gencode.c sim/mn10300/interp.c sim/mn10300/mn10300.dc
Diffstat (limited to 'sim/arm/armemu.c')
-rw-r--r--sim/arm/armemu.c4840
1 files changed, 0 insertions, 4840 deletions
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
deleted file mode 100644
index ebc6aed..0000000
--- a/sim/arm/armemu.c
+++ /dev/null
@@ -1,4840 +0,0 @@
-/* armemu.c -- Main instruction emulation: ARM7 Instruction Emulator.
- Copyright (C) 1994 Advanced RISC Machines Ltd.
- Modifications to add arch. v4 support by <jsmith@cygnus.com>.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-
-#include "armdefs.h"
-#include "armemu.h"
-#include "armos.h"
-
-static ARMword GetDPRegRHS (ARMul_State *, ARMword);
-static ARMword GetDPSRegRHS (ARMul_State *, ARMword);
-static void WriteR15 (ARMul_State *, ARMword);
-static void WriteSR15 (ARMul_State *, ARMword);
-static void WriteR15Branch (ARMul_State *, ARMword);
-static ARMword GetLSRegRHS (ARMul_State *, ARMword);
-static ARMword GetLS7RHS (ARMul_State *, ARMword);
-static unsigned LoadWord (ARMul_State *, ARMword, ARMword);
-static unsigned LoadHalfWord (ARMul_State *, ARMword, ARMword, int);
-static unsigned LoadByte (ARMul_State *, ARMword, ARMword, int);
-static unsigned StoreWord (ARMul_State *, ARMword, ARMword);
-static unsigned StoreHalfWord (ARMul_State *, ARMword, ARMword);
-static unsigned StoreByte (ARMul_State *, ARMword, ARMword);
-static void LoadMult (ARMul_State *, ARMword, ARMword, ARMword);
-static void StoreMult (ARMul_State *, ARMword, ARMword, ARMword);
-static void LoadSMult (ARMul_State *, ARMword, ARMword, ARMword);
-static void StoreSMult (ARMul_State *, ARMword, ARMword, ARMword);
-static unsigned Multiply64 (ARMul_State *, ARMword, int, int);
-static unsigned MultiplyAdd64 (ARMul_State *, ARMword, int, int);
-static void Handle_Load_Double (ARMul_State *, ARMword);
-static void Handle_Store_Double (ARMul_State *, ARMword);
-
-#define LUNSIGNED (0) /* unsigned operation */
-#define LSIGNED (1) /* signed operation */
-#define LDEFAULT (0) /* default : do nothing */
-#define LSCC (1) /* set condition codes on result */
-
-#ifdef NEED_UI_LOOP_HOOK
-/* How often to run the ui_loop update, when in use. */
-#define UI_LOOP_POLL_INTERVAL 0x32000
-
-/* Counter for the ui_loop_hook update. */
-static long ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
-
-/* Actual hook to call to run through gdb's gui event loop. */
-extern int (*ui_loop_hook) (int);
-#endif /* NEED_UI_LOOP_HOOK */
-
-extern int stop_simulator;
-
-/* Short-hand macros for LDR/STR. */
-
-/* Store post decrement writeback. */
-#define SHDOWNWB() \
- lhs = LHS ; \
- if (StoreHalfWord (state, instr, lhs)) \
- LSBase = lhs - GetLS7RHS (state, instr);
-
-/* Store post increment writeback. */
-#define SHUPWB() \
- lhs = LHS ; \
- if (StoreHalfWord (state, instr, lhs)) \
- LSBase = lhs + GetLS7RHS (state, instr);
-
-/* Store pre decrement. */
-#define SHPREDOWN() \
- (void)StoreHalfWord (state, instr, LHS - GetLS7RHS (state, instr));
-
-/* Store pre decrement writeback. */
-#define SHPREDOWNWB() \
- temp = LHS - GetLS7RHS (state, instr); \
- if (StoreHalfWord (state, instr, temp)) \
- LSBase = temp;
-
-/* Store pre increment. */
-#define SHPREUP() \
- (void)StoreHalfWord (state, instr, LHS + GetLS7RHS (state, instr));
-
-/* Store pre increment writeback. */
-#define SHPREUPWB() \
- temp = LHS + GetLS7RHS (state, instr); \
- if (StoreHalfWord (state, instr, temp)) \
- LSBase = temp;
-
-/* Load post decrement writeback. */
-#define LHPOSTDOWN() \
-{ \
- int done = 1; \
- lhs = LHS; \
- temp = lhs - GetLS7RHS (state, instr); \
- \
- switch (BITS (5, 6)) \
- { \
- case 1: /* H */ \
- if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \
- LSBase = temp; \
- break; \
- case 2: /* SB */ \
- if (LoadByte (state, instr, lhs, LSIGNED)) \
- LSBase = temp; \
- break; \
- case 3: /* SH */ \
- if (LoadHalfWord (state, instr, lhs, LSIGNED)) \
- LSBase = temp; \
- break; \
- case 0: /* SWP handled elsewhere. */ \
- default: \
- done = 0; \
- break; \
- } \
- if (done) \
- break; \
-}
-
-/* Load post increment writeback. */
-#define LHPOSTUP() \
-{ \
- int done = 1; \
- lhs = LHS; \
- temp = lhs + GetLS7RHS (state, instr); \
- \
- switch (BITS (5, 6)) \
- { \
- case 1: /* H */ \
- if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \
- LSBase = temp; \
- break; \
- case 2: /* SB */ \
- if (LoadByte (state, instr, lhs, LSIGNED)) \
- LSBase = temp; \
- break; \
- case 3: /* SH */ \
- if (LoadHalfWord (state, instr, lhs, LSIGNED)) \
- LSBase = temp; \
- break; \
- case 0: /* SWP handled elsewhere. */ \
- default: \
- done = 0; \
- break; \
- } \
- if (done) \
- break; \
-}
-
-/* Load pre decrement. */
-#define LHPREDOWN() \
-{ \
- int done = 1; \
- \
- temp = LHS - GetLS7RHS (state, instr); \
- switch (BITS (5, 6)) \
- { \
- case 1: /* H */ \
- (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \
- break; \
- case 2: /* SB */ \
- (void) LoadByte (state, instr, temp, LSIGNED); \
- break; \
- case 3: /* SH */ \
- (void) LoadHalfWord (state, instr, temp, LSIGNED); \
- break; \
- case 0: \
- /* SWP handled elsewhere. */ \
- default: \
- done = 0; \
- break; \
- } \
- if (done) \
- break; \
-}
-
-/* Load pre decrement writeback. */
-#define LHPREDOWNWB() \
-{ \
- int done = 1; \
- \
- temp = LHS - GetLS7RHS (state, instr); \
- switch (BITS (5, 6)) \
- { \
- case 1: /* H */ \
- if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \
- LSBase = temp; \
- break; \
- case 2: /* SB */ \
- if (LoadByte (state, instr, temp, LSIGNED)) \
- LSBase = temp; \
- break; \
- case 3: /* SH */ \
- if (LoadHalfWord (state, instr, temp, LSIGNED)) \
- LSBase = temp; \
- break; \
- case 0: \
- /* SWP handled elsewhere. */ \
- default: \
- done = 0; \
- break; \
- } \
- if (done) \
- break; \
-}
-
-/* Load pre increment. */
-#define LHPREUP() \
-{ \
- int done = 1; \
- \
- temp = LHS + GetLS7RHS (state, instr); \
- switch (BITS (5, 6)) \
- { \
- case 1: /* H */ \
- (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \
- break; \
- case 2: /* SB */ \
- (void) LoadByte (state, instr, temp, LSIGNED); \
- break; \
- case 3: /* SH */ \
- (void) LoadHalfWord (state, instr, temp, LSIGNED); \
- break; \
- case 0: \
- /* SWP handled elsewhere. */ \
- default: \
- done = 0; \
- break; \
- } \
- if (done) \
- break; \
-}
-
-/* Load pre increment writeback. */
-#define LHPREUPWB() \
-{ \
- int done = 1; \
- \
- temp = LHS + GetLS7RHS (state, instr); \
- switch (BITS (5, 6)) \
- { \
- case 1: /* H */ \
- if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \
- LSBase = temp; \
- break; \
- case 2: /* SB */ \
- if (LoadByte (state, instr, temp, LSIGNED)) \
- LSBase = temp; \
- break; \
- case 3: /* SH */ \
- if (LoadHalfWord (state, instr, temp, LSIGNED)) \
- LSBase = temp; \
- break; \
- case 0: \
- /* SWP handled elsewhere. */ \
- default: \
- done = 0; \
- break; \
- } \
- if (done) \
- break; \
-}
-
-/* EMULATION of ARM6. */
-
-/* The PC pipeline value depends on whether ARM
- or Thumb instructions are being executed. */
-ARMword isize;
-
-ARMword
-#ifdef MODE32
-ARMul_Emulate32 (ARMul_State * state)
-#else
-ARMul_Emulate26 (ARMul_State * state)
-#endif
-{
- ARMword instr; /* The current instruction. */
- ARMword dest = 0; /* Almost the DestBus. */
- ARMword temp; /* Ubiquitous third hand. */
- ARMword pc = 0; /* The address of the current instruction. */
- ARMword lhs; /* Almost the ABus and BBus. */
- ARMword rhs;
- ARMword decoded = 0; /* Instruction pipeline. */
- ARMword loaded = 0;
-
- /* Execute the next instruction. */
-
- if (state->NextInstr < PRIMEPIPE)
- {
- decoded = state->decoded;
- loaded = state->loaded;
- pc = state->pc;
- }
-
- do
- {
- /* Just keep going. */
- isize = INSN_SIZE;
-
- switch (state->NextInstr)
- {
- case SEQ:
- /* Advance the pipeline, and an S cycle. */
- state->Reg[15] += isize;
- pc += isize;
- instr = decoded;
- decoded = loaded;
- loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize);
- break;
-
- case NONSEQ:
- /* Advance the pipeline, and an N cycle. */
- state->Reg[15] += isize;
- pc += isize;
- instr = decoded;
- decoded = loaded;
- loaded = ARMul_LoadInstrN (state, pc + (isize * 2), isize);
- NORMALCYCLE;
- break;
-
- case PCINCEDSEQ:
- /* Program counter advanced, and an S cycle. */
- pc += isize;
- instr = decoded;
- decoded = loaded;
- loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize);
- NORMALCYCLE;
- break;
-
- case PCINCEDNONSEQ:
- /* Program counter advanced, and an N cycle. */
- pc += isize;
- instr = decoded;
- decoded = loaded;
- loaded = ARMul_LoadInstrN (state, pc + (isize * 2), isize);
- NORMALCYCLE;
- break;
-
- case RESUME:
- /* The program counter has been changed. */
- pc = state->Reg[15];
-#ifndef MODE32
- pc = pc & R15PCBITS;
-#endif
- state->Reg[15] = pc + (isize * 2);
- state->Aborted = 0;
- instr = ARMul_ReLoadInstr (state, pc, isize);
- decoded = ARMul_ReLoadInstr (state, pc + isize, isize);
- loaded = ARMul_ReLoadInstr (state, pc + isize * 2, isize);
- NORMALCYCLE;
- break;
-
- default:
- /* The program counter has been changed. */
- pc = state->Reg[15];
-#ifndef MODE32
- pc = pc & R15PCBITS;
-#endif
- state->Reg[15] = pc + (isize * 2);
- state->Aborted = 0;
- instr = ARMul_LoadInstrN (state, pc, isize);
- decoded = ARMul_LoadInstrS (state, pc + (isize), isize);
- loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize);
- NORMALCYCLE;
- break;
- }
-
- if (state->EventSet)
- ARMul_EnvokeEvent (state);
-#if 0
- /* Enable this for a helpful bit of debugging when tracing is needed. */
- fprintf (stderr, "pc: %x, instr: %x\n", pc & ~1, instr);
- if (instr == 0)
- abort ();
-#endif
-
- if (state->Exception)
- {
- /* Any exceptions ? */
- if (state->NresetSig == LOW)
- {
- ARMul_Abort (state, ARMul_ResetV);
- break;
- }
- else if (!state->NfiqSig && !FFLAG)
- {
- ARMul_Abort (state, ARMul_FIQV);
- break;
- }
- else if (!state->NirqSig && !IFLAG)
- {
- ARMul_Abort (state, ARMul_IRQV);
- break;
- }
- }
-
- if (state->CallDebug > 0)
- {
- instr = ARMul_Debug (state, pc, instr);
- if (state->Emulate < ONCE)
- {
- state->NextInstr = RESUME;
- break;
- }
- if (state->Debug)
- {
- fprintf (stderr, "sim: At %08lx Instr %08lx Mode %02lx\n", pc, instr,
- state->Mode);
- (void) fgetc (stdin);
- }
- }
- else if (state->Emulate < ONCE)
- {
- state->NextInstr = RESUME;
- break;
- }
-
- state->NumInstrs++;
-
-#ifdef MODET
- /* Provide Thumb instruction decoding. If the processor is in Thumb
- mode, then we can simply decode the Thumb instruction, and map it
- to the corresponding ARM instruction (by directly loading the
- instr variable, and letting the normal ARM simulator
- execute). There are some caveats to ensure that the correct
- pipelined PC value is used when executing Thumb code, and also for
- dealing with the BL instruction. */
- if (TFLAG)
- {
- ARMword new;
-
- /* Check if in Thumb mode. */
- switch (ARMul_ThumbDecode (state, pc, instr, &new))
- {
- case t_undefined:
- /* This is a Thumb instruction. */
- ARMul_UndefInstr (state, instr);
- goto donext;
-
- case t_branch:
- /* Already processed. */
- goto donext;
-
- case t_decoded:
- /* ARM instruction available. */
- instr = new;
- /* So continue instruction decoding. */
- break;
- default:
- break;
- }
- }
-#endif
-
- /* Check the condition codes. */
- if ((temp = TOPBITS (28)) == AL)
- /* Vile deed in the need for speed. */
- goto mainswitch;
-
- /* Check the condition code. */
- switch ((int) TOPBITS (28))
- {
- case AL:
- temp = TRUE;
- break;
- case NV:
- if (state->is_v5)
- {
- if (BITS (25, 27) == 5) /* BLX(1) */
- {
- ARMword dest;
-
- state->Reg[14] = pc + 4;
-
- dest = pc + 8 + 1; /* Force entry into Thumb mode. */
- if (BIT (23))
- dest += (NEGBRANCH + (BIT (24) << 1));
- else
- dest += POSBRANCH + (BIT (24) << 1);
-
- WriteR15Branch (state, dest);
- goto donext;
- }
- else if ((instr & 0xFC70F000) == 0xF450F000)
- /* The PLD instruction. Ignored. */
- goto donext;
- else
- /* UNDEFINED in v5, UNPREDICTABLE in v3, v4, non executed in v1, v2. */
- ARMul_UndefInstr (state, instr);
- }
- temp = FALSE;
- break;
- case EQ:
- temp = ZFLAG;
- break;
- case NE:
- temp = !ZFLAG;
- break;
- case VS:
- temp = VFLAG;
- break;
- case VC:
- temp = !VFLAG;
- break;
- case MI:
- temp = NFLAG;
- break;
- case PL:
- temp = !NFLAG;
- break;
- case CS:
- temp = CFLAG;
- break;
- case CC:
- temp = !CFLAG;
- break;
- case HI:
- temp = (CFLAG && !ZFLAG);
- break;
- case LS:
- temp = (!CFLAG || ZFLAG);
- break;
- case GE:
- temp = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG));
- break;
- case LT:
- temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG));
- break;
- case GT:
- temp = ((!NFLAG && !VFLAG && !ZFLAG) || (NFLAG && VFLAG && !ZFLAG));
- break;
- case LE:
- temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG;
- break;
- } /* cc check */
-
- /* Handle the Clock counter here. */
- if (state->is_XScale)
- {
- ARMword cp14r0 = state->CPRead[14] (state, 0, 0);
-
- if (cp14r0 && ARMul_CP14_R0_ENABLE)
- {
- unsigned long newcycles, nowtime = ARMul_Time(state);
-
- newcycles = nowtime - state->LastTime;
- state->LastTime = nowtime;
- if (cp14r0 && ARMul_CP14_R0_CCD)
- {
- if (state->CP14R0_CCD == -1)
- state->CP14R0_CCD = newcycles;
- else
- state->CP14R0_CCD += newcycles;
- if (state->CP14R0_CCD >= 64)
- {
- newcycles = 0;
- while (state->CP14R0_CCD >= 64)
- state->CP14R0_CCD -= 64, newcycles++;
- goto check_PMUintr;
- }
- }
- else
- {
- ARMword cp14r1;
- int do_int = 0;
-
- state->CP14R0_CCD = -1;
-check_PMUintr:
- cp14r0 |= ARMul_CP14_R0_FLAG2;
- (void) state->CPWrite[14] (state, 0, cp14r0);
-
- cp14r1 = state->CPRead[14] (state, 1, 0);
-
- /* Coded like this for portability. */
- while (newcycles)
- {
- if (cp14r1 == 0xffffffff)
- {
- cp14r1 = 0;
- do_int = 1;
- }
- else
- cp14r1++;
- newcycles--;
- }
- (void) state->CPWrite[14] (state, 1, cp14r1);
- if (do_int && (cp14r0 & ARMul_CP14_R0_INTEN2))
- {
- if (state->CPRead[13] (state, 8, 0)
- && ARMul_CP13_R8_PMUS)
- ARMul_Abort (state, ARMul_FIQV);
- else
- ARMul_Abort (state, ARMul_IRQV);
- }
- }
- }
- }
-
- /* Handle hardware instructions breakpoints here. */
- if (state->is_XScale)
- {
- if ((pc | 3) == (read_cp15_reg (14, 0, 8) | 2)
- || (pc | 3) == (read_cp15_reg (14, 0, 9) | 2))
- {
- if (XScale_debug_moe (state, ARMul_CP14_R10_MOE_IB))
- ARMul_OSHandleSWI (state, SWI_Breakpoint);
- }
- }
-
- /* Actual execution of instructions begins here. */
-
- if (temp)
- {
- /* If the condition codes don't match, stop here. */
- mainswitch:
-
- if (state->is_XScale)
- {
- if (BIT (20) == 0 && BITS (25, 27) == 0)
- {
- if (BITS (4, 7) == 0xD)
- {
- /* XScale Load Consecutive insn. */
- ARMword temp = GetLS7RHS (state, instr);
- ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
- ARMword addr = BIT (24) ? temp2 : LHS;
-
- if (BIT (12))
- ARMul_UndefInstr (state, instr);
- else if (addr & 7)
- /* Alignment violation. */
- ARMul_Abort (state, ARMul_DataAbortV);
- else
- {
- int wb = BIT (21) || (! BIT (24));
-
- state->Reg[BITS (12, 15)] =
- ARMul_LoadWordN (state, addr);
- state->Reg[BITS (12, 15) + 1] =
- ARMul_LoadWordN (state, addr + 4);
- if (wb)
- LSBase = temp2;
- }
-
- goto donext;
- }
- else if (BITS (4, 7) == 0xF)
- {
- /* XScale Store Consecutive insn. */
- ARMword temp = GetLS7RHS (state, instr);
- ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
- ARMword addr = BIT (24) ? temp2 : LHS;
-
- if (BIT (12))
- ARMul_UndefInstr (state, instr);
- else if (addr & 7)
- /* Alignment violation. */
- ARMul_Abort (state, ARMul_DataAbortV);
- else
- {
- ARMul_StoreWordN (state, addr,
- state->Reg[BITS (12, 15)]);
- ARMul_StoreWordN (state, addr + 4,
- state->Reg[BITS (12, 15) + 1]);
-
- if (BIT (21)|| ! BIT (24))
- LSBase = temp2;
- }
-
- goto donext;
- }
- }
- }
-
- switch ((int) BITS (20, 27))
- {
- /* Data Processing Register RHS Instructions. */
-
- case 0x00: /* AND reg and MUL */
-#ifdef MODET
- if (BITS (4, 11) == 0xB)
- {
- /* STRH register offset, no write-back, down, post indexed. */
- SHDOWNWB ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- if (BITS (4, 7) == 9)
- { /* MUL */
- rhs = state->Reg[MULRHSReg];
- if (MULLHSReg == MULDESTReg)
- {
- UNDEF_MULDestEQOp1;
- state->Reg[MULDESTReg] = 0;
- }
- else if (MULDESTReg != 15)
- state->Reg[MULDESTReg] = state->Reg[MULLHSReg] * rhs;
- else
- {
- UNDEF_MULPCDest;
- }
- for (dest = 0, temp = 0; dest < 32; dest++)
- if (rhs & (1L << dest))
- temp = dest; /* mult takes this many/2 I cycles */
- ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
- }
- else
- { /* AND reg */
- rhs = DPRegRHS;
- dest = LHS & rhs;
- WRITEDEST (dest);
- }
- break;
-
- case 0x01: /* ANDS reg and MULS */
-#ifdef MODET
- if ((BITS (4, 11) & 0xF9) == 0x9)
- {
- /* LDR register offset, no write-back, down, post indexed */
- LHPOSTDOWN ();
- /* fall through to rest of decoding */
- }
-#endif
- if (BITS (4, 7) == 9)
- { /* MULS */
- rhs = state->Reg[MULRHSReg];
- if (MULLHSReg == MULDESTReg)
- {
- UNDEF_MULDestEQOp1;
- state->Reg[MULDESTReg] = 0;
- CLEARN;
- SETZ;
- }
- else if (MULDESTReg != 15)
- {
- dest = state->Reg[MULLHSReg] * rhs;
- ARMul_NegZero (state, dest);
- state->Reg[MULDESTReg] = dest;
- }
- else
- {
- UNDEF_MULPCDest;
- }
- for (dest = 0, temp = 0; dest < 32; dest++)
- if (rhs & (1L << dest))
- temp = dest; /* mult takes this many/2 I cycles */
- ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
- }
- else
- { /* ANDS reg */
- rhs = DPSRegRHS;
- dest = LHS & rhs;
- WRITESDEST (dest);
- }
- break;
-
- case 0x02: /* EOR reg and MLA */
-#ifdef MODET
- if (BITS (4, 11) == 0xB)
- {
- /* STRH register offset, write-back, down, post indexed */
- SHDOWNWB ();
- break;
- }
-#endif
- if (BITS (4, 7) == 9)
- { /* MLA */
- rhs = state->Reg[MULRHSReg];
- if (MULLHSReg == MULDESTReg)
- {
- UNDEF_MULDestEQOp1;
- state->Reg[MULDESTReg] = state->Reg[MULACCReg];
- }
- else if (MULDESTReg != 15)
- state->Reg[MULDESTReg] =
- state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg];
- else
- {
- UNDEF_MULPCDest;
- }
- for (dest = 0, temp = 0; dest < 32; dest++)
- if (rhs & (1L << dest))
- temp = dest; /* mult takes this many/2 I cycles */
- ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
- }
- else
- {
- rhs = DPRegRHS;
- dest = LHS ^ rhs;
- WRITEDEST (dest);
- }
- break;
-
- case 0x03: /* EORS reg and MLAS */
-#ifdef MODET
- if ((BITS (4, 11) & 0xF9) == 0x9)
- {
- /* LDR register offset, write-back, down, post-indexed */
- LHPOSTDOWN ();
- /* fall through to rest of the decoding */
- }
-#endif
- if (BITS (4, 7) == 9)
- { /* MLAS */
- rhs = state->Reg[MULRHSReg];
- if (MULLHSReg == MULDESTReg)
- {
- UNDEF_MULDestEQOp1;
- dest = state->Reg[MULACCReg];
- ARMul_NegZero (state, dest);
- state->Reg[MULDESTReg] = dest;
- }
- else if (MULDESTReg != 15)
- {
- dest =
- state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg];
- ARMul_NegZero (state, dest);
- state->Reg[MULDESTReg] = dest;
- }
- else
- {
- UNDEF_MULPCDest;
- }
- for (dest = 0, temp = 0; dest < 32; dest++)
- if (rhs & (1L << dest))
- temp = dest; /* mult takes this many/2 I cycles */
- ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
- }
- else
- { /* EORS Reg */
- rhs = DPSRegRHS;
- dest = LHS ^ rhs;
- WRITESDEST (dest);
- }
- break;
-
- case 0x04: /* SUB reg */
-#ifdef MODET
- if (BITS (4, 7) == 0xB)
- {
- /* STRH immediate offset, no write-back, down, post indexed */
- SHDOWNWB ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- rhs = DPRegRHS;
- dest = LHS - rhs;
- WRITEDEST (dest);
- break;
-
- case 0x05: /* SUBS reg */
-#ifdef MODET
- if ((BITS (4, 7) & 0x9) == 0x9)
- {
- /* LDR immediate offset, no write-back, down, post indexed */
- LHPOSTDOWN ();
- /* fall through to the rest of the instruction decoding */
- }
-#endif
- lhs = LHS;
- rhs = DPRegRHS;
- dest = lhs - rhs;
- if ((lhs >= rhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, lhs, rhs, dest);
- ARMul_SubOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x06: /* RSB reg */
-#ifdef MODET
- if (BITS (4, 7) == 0xB)
- {
- /* STRH immediate offset, write-back, down, post indexed */
- SHDOWNWB ();
- break;
- }
-#endif
- rhs = DPRegRHS;
- dest = rhs - LHS;
- WRITEDEST (dest);
- break;
-
- case 0x07: /* RSBS reg */
-#ifdef MODET
- if ((BITS (4, 7) & 0x9) == 0x9)
- {
- /* LDR immediate offset, write-back, down, post indexed */
- LHPOSTDOWN ();
- /* fall through to remainder of instruction decoding */
- }
-#endif
- lhs = LHS;
- rhs = DPRegRHS;
- dest = rhs - lhs;
- if ((rhs >= lhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, rhs, lhs, dest);
- ARMul_SubOverflow (state, rhs, lhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x08: /* ADD reg */
-#ifdef MODET
- if (BITS (4, 11) == 0xB)
- {
- /* STRH register offset, no write-back, up, post indexed */
- SHUPWB ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
-#ifdef MODET
- if (BITS (4, 7) == 0x9)
- { /* MULL */
- /* 32x32 = 64 */
- ARMul_Icycles (state,
- Multiply64 (state, instr, LUNSIGNED,
- LDEFAULT), 0L);
- break;
- }
-#endif
- rhs = DPRegRHS;
- dest = LHS + rhs;
- WRITEDEST (dest);
- break;
-
- case 0x09: /* ADDS reg */
-#ifdef MODET
- if ((BITS (4, 11) & 0xF9) == 0x9)
- {
- /* LDR register offset, no write-back, up, post indexed */
- LHPOSTUP ();
- /* fall through to remaining instruction decoding */
- }
-#endif
-#ifdef MODET
- if (BITS (4, 7) == 0x9)
- { /* MULL */
- /* 32x32=64 */
- ARMul_Icycles (state,
- Multiply64 (state, instr, LUNSIGNED, LSCC),
- 0L);
- break;
- }
-#endif
- lhs = LHS;
- rhs = DPRegRHS;
- dest = lhs + rhs;
- ASSIGNZ (dest == 0);
- if ((lhs | rhs) >> 30)
- { /* possible C,V,N to set */
- ASSIGNN (NEG (dest));
- ARMul_AddCarry (state, lhs, rhs, dest);
- ARMul_AddOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARN;
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x0a: /* ADC reg */
-#ifdef MODET
- if (BITS (4, 11) == 0xB)
- {
- /* STRH register offset, write-back, up, post-indexed */
- SHUPWB ();
- break;
- }
-#endif
-#ifdef MODET
- if (BITS (4, 7) == 0x9)
- { /* MULL */
- /* 32x32=64 */
- ARMul_Icycles (state,
- MultiplyAdd64 (state, instr, LUNSIGNED,
- LDEFAULT), 0L);
- break;
- }
-#endif
- rhs = DPRegRHS;
- dest = LHS + rhs + CFLAG;
- WRITEDEST (dest);
- break;
-
- case 0x0b: /* ADCS reg */
-#ifdef MODET
- if ((BITS (4, 11) & 0xF9) == 0x9)
- {
- /* LDR register offset, write-back, up, post indexed */
- LHPOSTUP ();
- /* fall through to remaining instruction decoding */
- }
-#endif
-#ifdef MODET
- if (BITS (4, 7) == 0x9)
- { /* MULL */
- /* 32x32=64 */
- ARMul_Icycles (state,
- MultiplyAdd64 (state, instr, LUNSIGNED,
- LSCC), 0L);
- break;
- }
-#endif
- lhs = LHS;
- rhs = DPRegRHS;
- dest = lhs + rhs + CFLAG;
- ASSIGNZ (dest == 0);
- if ((lhs | rhs) >> 30)
- { /* possible C,V,N to set */
- ASSIGNN (NEG (dest));
- ARMul_AddCarry (state, lhs, rhs, dest);
- ARMul_AddOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARN;
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x0c: /* SBC reg */
-#ifdef MODET
- if (BITS (4, 7) == 0xB)
- {
- /* STRH immediate offset, no write-back, up post indexed */
- SHUPWB ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
-#ifdef MODET
- if (BITS (4, 7) == 0x9)
- { /* MULL */
- /* 32x32=64 */
- ARMul_Icycles (state,
- Multiply64 (state, instr, LSIGNED, LDEFAULT),
- 0L);
- break;
- }
-#endif
- rhs = DPRegRHS;
- dest = LHS - rhs - !CFLAG;
- WRITEDEST (dest);
- break;
-
- case 0x0d: /* SBCS reg */
-#ifdef MODET
- if ((BITS (4, 7) & 0x9) == 0x9)
- {
- /* LDR immediate offset, no write-back, up, post indexed */
- LHPOSTUP ();
- }
-#endif
-#ifdef MODET
- if (BITS (4, 7) == 0x9)
- { /* MULL */
- /* 32x32=64 */
- ARMul_Icycles (state,
- Multiply64 (state, instr, LSIGNED, LSCC),
- 0L);
- break;
- }
-#endif
- lhs = LHS;
- rhs = DPRegRHS;
- dest = lhs - rhs - !CFLAG;
- if ((lhs >= rhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, lhs, rhs, dest);
- ARMul_SubOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x0e: /* RSC reg */
-#ifdef MODET
- if (BITS (4, 7) == 0xB)
- {
- /* STRH immediate offset, write-back, up, post indexed */
- SHUPWB ();
- break;
- }
-#endif
-#ifdef MODET
- if (BITS (4, 7) == 0x9)
- { /* MULL */
- /* 32x32=64 */
- ARMul_Icycles (state,
- MultiplyAdd64 (state, instr, LSIGNED,
- LDEFAULT), 0L);
- break;
- }
-#endif
- rhs = DPRegRHS;
- dest = rhs - LHS - !CFLAG;
- WRITEDEST (dest);
- break;
-
- case 0x0f: /* RSCS reg */
-#ifdef MODET
- if ((BITS (4, 7) & 0x9) == 0x9)
- {
- /* LDR immediate offset, write-back, up, post indexed */
- LHPOSTUP ();
- /* fall through to remaining instruction decoding */
- }
-#endif
-#ifdef MODET
- if (BITS (4, 7) == 0x9)
- { /* MULL */
- /* 32x32=64 */
- ARMul_Icycles (state,
- MultiplyAdd64 (state, instr, LSIGNED, LSCC),
- 0L);
- break;
- }
-#endif
- lhs = LHS;
- rhs = DPRegRHS;
- dest = rhs - lhs - !CFLAG;
- if ((rhs >= lhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, rhs, lhs, dest);
- ARMul_SubOverflow (state, rhs, lhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x10: /* TST reg and MRS CPSR and SWP word */
- if (state->is_v5e)
- {
- if (BIT (4) == 0 && BIT (7) == 1)
- {
- /* ElSegundo SMLAxy insn. */
- ARMword op1 = state->Reg[BITS (0, 3)];
- ARMword op2 = state->Reg[BITS (8, 11)];
- ARMword Rn = state->Reg[BITS (12, 15)];
-
- if (BIT (5))
- op1 >>= 16;
- if (BIT (6))
- op2 >>= 16;
- op1 &= 0xFFFF;
- op2 &= 0xFFFF;
- if (op1 & 0x8000)
- op1 -= 65536;
- if (op2 & 0x8000)
- op2 -= 65536;
- op1 *= op2;
-
- if (AddOverflow (op1, Rn, op1 + Rn))
- SETS;
- state->Reg[BITS (16, 19)] = op1 + Rn;
- break;
- }
-
- if (BITS (4, 11) == 5)
- {
- /* ElSegundo QADD insn. */
- ARMword op1 = state->Reg[BITS (0, 3)];
- ARMword op2 = state->Reg[BITS (16, 19)];
- ARMword result = op1 + op2;
- if (AddOverflow (op1, op2, result))
- {
- result = POS (result) ? 0x80000000 : 0x7fffffff;
- SETS;
- }
- state->Reg[BITS (12, 15)] = result;
- break;
- }
- }
-#ifdef MODET
- if (BITS (4, 11) == 0xB)
- {
- /* STRH register offset, no write-back, down, pre indexed */
- SHPREDOWN ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- if (BITS (4, 11) == 9)
- { /* SWP */
- UNDEF_SWPPC;
- temp = LHS;
- BUSUSEDINCPCS;
-#ifndef MODE32
- if (VECTORACCESS (temp) || ADDREXCEPT (temp))
- {
- INTERNALABORT (temp);
- (void) ARMul_LoadWordN (state, temp);
- (void) ARMul_LoadWordN (state, temp);
- }
- else
-#endif
- dest = ARMul_SwapWord (state, temp, state->Reg[RHSReg]);
- if (temp & 3)
- DEST = ARMul_Align (state, temp, dest);
- else
- DEST = dest;
- if (state->abortSig || state->Aborted)
- {
- TAKEABORT;
- }
- }
- else if ((BITS (0, 11) == 0) && (LHSReg == 15))
- { /* MRS CPSR */
- UNDEF_MRSPC;
- DEST = ECC | EINT | EMODE;
- }
- else
- {
- UNDEF_Test;
- }
- break;
-
- case 0x11: /* TSTP reg */
-#ifdef MODET
- if ((BITS (4, 11) & 0xF9) == 0x9)
- {
- /* LDR register offset, no write-back, down, pre indexed */
- LHPREDOWN ();
- /* continue with remaining instruction decode */
- }
-#endif
- if (DESTReg == 15)
- { /* TSTP reg */
-#ifdef MODE32
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
-#else
- rhs = DPRegRHS;
- temp = LHS & rhs;
- SETR15PSR (temp);
-#endif
- }
- else
- { /* TST reg */
- rhs = DPSRegRHS;
- dest = LHS & rhs;
- ARMul_NegZero (state, dest);
- }
- break;
-
- case 0x12: /* TEQ reg and MSR reg to CPSR (ARM6) */
- if (state->is_v5)
- {
- if (BITS (4, 7) == 3)
- {
- /* BLX(2) */
- ARMword temp;
-
- if (TFLAG)
- temp = (pc + 2) | 1;
- else
- temp = pc + 4;
-
- WriteR15Branch (state, state->Reg[RHSReg]);
- state->Reg[14] = temp;
- break;
- }
- }
-
- if (state->is_v5e)
- {
- if (BIT (4) == 0 && BIT (7) == 1
- && (BIT (5) == 0 || BITS (12, 15) == 0))
- {
- /* ElSegundo SMLAWy/SMULWy insn. */
- unsigned long long op1 = state->Reg[BITS (0, 3)];
- unsigned long long op2 = state->Reg[BITS (8, 11)];
- unsigned long long result;
-
- if (BIT (6))
- op2 >>= 16;
- if (op1 & 0x80000000)
- op1 -= 1ULL << 32;
- op2 &= 0xFFFF;
- if (op2 & 0x8000)
- op2 -= 65536;
- result = (op1 * op2) >> 16;
-
- if (BIT (5) == 0)
- {
- ARMword Rn = state->Reg[BITS (12, 15)];
-
- if (AddOverflow (result, Rn, result + Rn))
- SETS;
- result += Rn;
- }
- state->Reg[BITS (16, 19)] = result;
- break;
- }
-
- if (BITS (4, 11) == 5)
- {
- /* ElSegundo QSUB insn. */
- ARMword op1 = state->Reg[BITS (0, 3)];
- ARMword op2 = state->Reg[BITS (16, 19)];
- ARMword result = op1 - op2;
-
- if (SubOverflow (op1, op2, result))
- {
- result = POS (result) ? 0x80000000 : 0x7fffffff;
- SETS;
- }
-
- state->Reg[BITS (12, 15)] = result;
- break;
- }
- }
-#ifdef MODET
- if (BITS (4, 11) == 0xB)
- {
- /* STRH register offset, write-back, down, pre indexed */
- SHPREDOWNWB ();
- break;
- }
- if (BITS (4, 27) == 0x12FFF1)
- {
- /* BX */
- WriteR15Branch (state, state->Reg[RHSReg]);
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- if (state->is_v5)
- {
- if (BITS (4, 7) == 0x7)
- {
- ARMword value;
- extern int SWI_vector_installed;
-
- /* Hardware is allowed to optionally override this
- instruction and treat it as a breakpoint. Since
- this is a simulator not hardware, we take the position
- that if a SWI vector was not installed, then an Abort
- vector was probably not installed either, and so
- normally this instruction would be ignored, even if an
- Abort is generated. This is a bad thing, since GDB
- uses this instruction for its breakpoints (at least in
- Thumb mode it does). So intercept the instruction here
- and generate a breakpoint SWI instead. */
- if (! SWI_vector_installed)
- ARMul_OSHandleSWI (state, SWI_Breakpoint);
- else
- {
- /* BKPT - normally this will cause an abort, but on the
- XScale we must check the DCSR. */
- XScale_set_fsr_far (state, ARMul_CP15_R5_MMU_EXCPT, pc);
- if (!XScale_debug_moe (state, ARMul_CP14_R10_MOE_BT))
- break;
- }
-
- /* Force the next instruction to be refetched. */
- state->NextInstr = RESUME;
- break;
- }
- }
- if (DESTReg == 15)
- {
- /* MSR reg to CPSR */
- UNDEF_MSRPC;
- temp = DPRegRHS;
-#ifdef MODET
- /* Don't allow TBIT to be set by MSR. */
- temp &= ~ TBIT;
-#endif
- ARMul_FixCPSR (state, instr, temp);
- }
- else
- {
- UNDEF_Test;
- }
- break;
-
- case 0x13: /* TEQP reg */
-#ifdef MODET
- if ((BITS (4, 11) & 0xF9) == 0x9)
- {
- /* LDR register offset, write-back, down, pre indexed. */
- LHPREDOWNWB ();
- /* Continue with remaining instruction decode. */
- }
-#endif
- if (DESTReg == 15)
- { /* TEQP reg */
-#ifdef MODE32
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
-#else
- rhs = DPRegRHS;
- temp = LHS ^ rhs;
- SETR15PSR (temp);
-#endif
- }
- else
- { /* TEQ Reg */
- rhs = DPSRegRHS;
- dest = LHS ^ rhs;
- ARMul_NegZero (state, dest);
- }
- break;
-
- case 0x14: /* CMP reg and MRS SPSR and SWP byte */
- if (state->is_v5e)
- {
- if (BIT (4) == 0 && BIT (7) == 1)
- {
- /* ElSegundo SMLALxy insn. */
- unsigned long long op1 = state->Reg[BITS (0, 3)];
- unsigned long long op2 = state->Reg[BITS (8, 11)];
- unsigned long long dest;
- unsigned long long result;
-
- if (BIT (5))
- op1 >>= 16;
- if (BIT (6))
- op2 >>= 16;
- op1 &= 0xFFFF;
- if (op1 & 0x8000)
- op1 -= 65536;
- op2 &= 0xFFFF;
- if (op2 & 0x8000)
- op2 -= 65536;
-
- dest = (unsigned long long) state->Reg[BITS (16, 19)] << 32;
- dest |= state->Reg[BITS (12, 15)];
- dest += op1 * op2;
- state->Reg[BITS (12, 15)] = dest;
- state->Reg[BITS (16, 19)] = dest >> 32;
- break;
- }
-
- if (BITS (4, 11) == 5)
- {
- /* ElSegundo QDADD insn. */
- ARMword op1 = state->Reg[BITS (0, 3)];
- ARMword op2 = state->Reg[BITS (16, 19)];
- ARMword op2d = op2 + op2;
- ARMword result;
-
- if (AddOverflow (op2, op2, op2d))
- {
- SETS;
- op2d = POS (op2d) ? 0x80000000 : 0x7fffffff;
- }
-
- result = op1 + op2d;
- if (AddOverflow (op1, op2d, result))
- {
- SETS;
- result = POS (result) ? 0x80000000 : 0x7fffffff;
- }
-
- state->Reg[BITS (12, 15)] = result;
- break;
- }
- }
-#ifdef MODET
- if (BITS (4, 7) == 0xB)
- {
- /* STRH immediate offset, no write-back, down, pre indexed. */
- SHPREDOWN ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- if (BITS (4, 11) == 9)
- { /* SWP */
- UNDEF_SWPPC;
- temp = LHS;
- BUSUSEDINCPCS;
-#ifndef MODE32
- if (VECTORACCESS (temp) || ADDREXCEPT (temp))
- {
- INTERNALABORT (temp);
- (void) ARMul_LoadByte (state, temp);
- (void) ARMul_LoadByte (state, temp);
- }
- else
-#endif
- DEST = ARMul_SwapByte (state, temp, state->Reg[RHSReg]);
- if (state->abortSig || state->Aborted)
- {
- TAKEABORT;
- }
- }
- else if ((BITS (0, 11) == 0) && (LHSReg == 15))
- { /* MRS SPSR */
- UNDEF_MRSPC;
- DEST = GETSPSR (state->Bank);
- }
- else
- {
- UNDEF_Test;
- }
- break;
-
- case 0x15: /* CMPP reg */
-#ifdef MODET
- if ((BITS (4, 7) & 0x9) == 0x9)
- {
- /* LDR immediate offset, no write-back, down, pre indexed */
- LHPREDOWN ();
- /* continue with remaining instruction decode */
- }
-#endif
- if (DESTReg == 15)
- { /* CMPP reg */
-#ifdef MODE32
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
-#else
- rhs = DPRegRHS;
- temp = LHS - rhs;
- SETR15PSR (temp);
-#endif
- }
- else
- { /* CMP reg */
- lhs = LHS;
- rhs = DPRegRHS;
- dest = lhs - rhs;
- ARMul_NegZero (state, dest);
- if ((lhs >= rhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, lhs, rhs, dest);
- ARMul_SubOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- }
- break;
-
- case 0x16: /* CMN reg and MSR reg to SPSR */
- if (state->is_v5e)
- {
- if (BIT (4) == 0 && BIT (7) == 1 && BITS (12, 15) == 0)
- {
- /* ElSegundo SMULxy insn. */
- ARMword op1 = state->Reg[BITS (0, 3)];
- ARMword op2 = state->Reg[BITS (8, 11)];
- ARMword Rn = state->Reg[BITS (12, 15)];
-
- if (BIT (5))
- op1 >>= 16;
- if (BIT (6))
- op2 >>= 16;
- op1 &= 0xFFFF;
- op2 &= 0xFFFF;
- if (op1 & 0x8000)
- op1 -= 65536;
- if (op2 & 0x8000)
- op2 -= 65536;
-
- state->Reg[BITS (16, 19)] = op1 * op2;
- break;
- }
-
- if (BITS (4, 11) == 5)
- {
- /* ElSegundo QDSUB insn. */
- ARMword op1 = state->Reg[BITS (0, 3)];
- ARMword op2 = state->Reg[BITS (16, 19)];
- ARMword op2d = op2 + op2;
- ARMword result;
-
- if (AddOverflow (op2, op2, op2d))
- {
- SETS;
- op2d = POS (op2d) ? 0x80000000 : 0x7fffffff;
- }
-
- result = op1 - op2d;
- if (SubOverflow (op1, op2d, result))
- {
- SETS;
- result = POS (result) ? 0x80000000 : 0x7fffffff;
- }
-
- state->Reg[BITS (12, 15)] = result;
- break;
- }
- }
-
- if (state->is_v5)
- {
- if (BITS (4, 11) == 0xF1 && BITS (16, 19) == 0xF)
- {
- /* ARM5 CLZ insn. */
- ARMword op1 = state->Reg[BITS (0, 3)];
- int result = 32;
-
- if (op1)
- for (result = 0; (op1 & 0x80000000) == 0; op1 <<= 1)
- result++;
-
- state->Reg[BITS (12, 15)] = result;
- break;
- }
- }
-#ifdef MODET
- if (BITS (4, 7) == 0xB)
- {
- /* STRH immediate offset, write-back, down, pre indexed */
- SHPREDOWNWB ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- if (DESTReg == 15)
- { /* MSR */
- UNDEF_MSRPC;
- ARMul_FixSPSR (state, instr, DPRegRHS);
- }
- else
- {
- UNDEF_Test;
- }
- break;
-
- case 0x17: /* CMNP reg */
-#ifdef MODET
- if ((BITS (4, 7) & 0x9) == 0x9)
- {
- /* LDR immediate offset, write-back, down, pre indexed */
- LHPREDOWNWB ();
- /* continue with remaining instruction decoding */
- }
-#endif
- if (DESTReg == 15)
- {
-#ifdef MODE32
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
-#else
- rhs = DPRegRHS;
- temp = LHS + rhs;
- SETR15PSR (temp);
-#endif
- break;
- }
- else
- { /* CMN reg */
- lhs = LHS;
- rhs = DPRegRHS;
- dest = lhs + rhs;
- ASSIGNZ (dest == 0);
- if ((lhs | rhs) >> 30)
- { /* possible C,V,N to set */
- ASSIGNN (NEG (dest));
- ARMul_AddCarry (state, lhs, rhs, dest);
- ARMul_AddOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARN;
- CLEARC;
- CLEARV;
- }
- }
- break;
-
- case 0x18: /* ORR reg */
-#ifdef MODET
- if (BITS (4, 11) == 0xB)
- {
- /* STRH register offset, no write-back, up, pre indexed */
- SHPREUP ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- rhs = DPRegRHS;
- dest = LHS | rhs;
- WRITEDEST (dest);
- break;
-
- case 0x19: /* ORRS reg */
-#ifdef MODET
- if ((BITS (4, 11) & 0xF9) == 0x9)
- {
- /* LDR register offset, no write-back, up, pre indexed */
- LHPREUP ();
- /* continue with remaining instruction decoding */
- }
-#endif
- rhs = DPSRegRHS;
- dest = LHS | rhs;
- WRITESDEST (dest);
- break;
-
- case 0x1a: /* MOV reg */
-#ifdef MODET
- if (BITS (4, 11) == 0xB)
- {
- /* STRH register offset, write-back, up, pre indexed */
- SHPREUPWB ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- dest = DPRegRHS;
- WRITEDEST (dest);
- break;
-
- case 0x1b: /* MOVS reg */
-#ifdef MODET
- if ((BITS (4, 11) & 0xF9) == 0x9)
- {
- /* LDR register offset, write-back, up, pre indexed */
- LHPREUPWB ();
- /* continue with remaining instruction decoding */
- }
-#endif
- dest = DPSRegRHS;
- WRITESDEST (dest);
- break;
-
- case 0x1c: /* BIC reg */
-#ifdef MODET
- if (BITS (4, 7) == 0xB)
- {
- /* STRH immediate offset, no write-back, up, pre indexed */
- SHPREUP ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- else if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- rhs = DPRegRHS;
- dest = LHS & ~rhs;
- WRITEDEST (dest);
- break;
-
- case 0x1d: /* BICS reg */
-#ifdef MODET
- if ((BITS (4, 7) & 0x9) == 0x9)
- {
- /* LDR immediate offset, no write-back, up, pre indexed */
- LHPREUP ();
- /* continue with instruction decoding */
- }
-#endif
- rhs = DPSRegRHS;
- dest = LHS & ~rhs;
- WRITESDEST (dest);
- break;
-
- case 0x1e: /* MVN reg */
-#ifdef MODET
- if (BITS (4, 7) == 0xB)
- {
- /* STRH immediate offset, write-back, up, pre indexed */
- SHPREUPWB ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- dest = ~DPRegRHS;
- WRITEDEST (dest);
- break;
-
- case 0x1f: /* MVNS reg */
-#ifdef MODET
- if ((BITS (4, 7) & 0x9) == 0x9)
- {
- /* LDR immediate offset, write-back, up, pre indexed */
- LHPREUPWB ();
- /* continue instruction decoding */
- }
-#endif
- dest = ~DPSRegRHS;
- WRITESDEST (dest);
- break;
-
-
- /* Data Processing Immediate RHS Instructions. */
-
- case 0x20: /* AND immed */
- dest = LHS & DPImmRHS;
- WRITEDEST (dest);
- break;
-
- case 0x21: /* ANDS immed */
- DPSImmRHS;
- dest = LHS & rhs;
- WRITESDEST (dest);
- break;
-
- case 0x22: /* EOR immed */
- dest = LHS ^ DPImmRHS;
- WRITEDEST (dest);
- break;
-
- case 0x23: /* EORS immed */
- DPSImmRHS;
- dest = LHS ^ rhs;
- WRITESDEST (dest);
- break;
-
- case 0x24: /* SUB immed */
- dest = LHS - DPImmRHS;
- WRITEDEST (dest);
- break;
-
- case 0x25: /* SUBS immed */
- lhs = LHS;
- rhs = DPImmRHS;
- dest = lhs - rhs;
- if ((lhs >= rhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, lhs, rhs, dest);
- ARMul_SubOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x26: /* RSB immed */
- dest = DPImmRHS - LHS;
- WRITEDEST (dest);
- break;
-
- case 0x27: /* RSBS immed */
- lhs = LHS;
- rhs = DPImmRHS;
- dest = rhs - lhs;
- if ((rhs >= lhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, rhs, lhs, dest);
- ARMul_SubOverflow (state, rhs, lhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x28: /* ADD immed */
- dest = LHS + DPImmRHS;
- WRITEDEST (dest);
- break;
-
- case 0x29: /* ADDS immed */
- lhs = LHS;
- rhs = DPImmRHS;
- dest = lhs + rhs;
- ASSIGNZ (dest == 0);
- if ((lhs | rhs) >> 30)
- { /* possible C,V,N to set */
- ASSIGNN (NEG (dest));
- ARMul_AddCarry (state, lhs, rhs, dest);
- ARMul_AddOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARN;
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x2a: /* ADC immed */
- dest = LHS + DPImmRHS + CFLAG;
- WRITEDEST (dest);
- break;
-
- case 0x2b: /* ADCS immed */
- lhs = LHS;
- rhs = DPImmRHS;
- dest = lhs + rhs + CFLAG;
- ASSIGNZ (dest == 0);
- if ((lhs | rhs) >> 30)
- { /* possible C,V,N to set */
- ASSIGNN (NEG (dest));
- ARMul_AddCarry (state, lhs, rhs, dest);
- ARMul_AddOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARN;
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x2c: /* SBC immed */
- dest = LHS - DPImmRHS - !CFLAG;
- WRITEDEST (dest);
- break;
-
- case 0x2d: /* SBCS immed */
- lhs = LHS;
- rhs = DPImmRHS;
- dest = lhs - rhs - !CFLAG;
- if ((lhs >= rhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, lhs, rhs, dest);
- ARMul_SubOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x2e: /* RSC immed */
- dest = DPImmRHS - LHS - !CFLAG;
- WRITEDEST (dest);
- break;
-
- case 0x2f: /* RSCS immed */
- lhs = LHS;
- rhs = DPImmRHS;
- dest = rhs - lhs - !CFLAG;
- if ((rhs >= lhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, rhs, lhs, dest);
- ARMul_SubOverflow (state, rhs, lhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x30: /* TST immed */
- UNDEF_Test;
- break;
-
- case 0x31: /* TSTP immed */
- if (DESTReg == 15)
- { /* TSTP immed */
-#ifdef MODE32
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
-#else
- temp = LHS & DPImmRHS;
- SETR15PSR (temp);
-#endif
- }
- else
- {
- DPSImmRHS; /* TST immed */
- dest = LHS & rhs;
- ARMul_NegZero (state, dest);
- }
- break;
-
- case 0x32: /* TEQ immed and MSR immed to CPSR */
- if (DESTReg == 15)
- { /* MSR immed to CPSR */
- ARMul_FixCPSR (state, instr, DPImmRHS);
- }
- else
- {
- UNDEF_Test;
- }
- break;
-
- case 0x33: /* TEQP immed */
- if (DESTReg == 15)
- { /* TEQP immed */
-#ifdef MODE32
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
-#else
- temp = LHS ^ DPImmRHS;
- SETR15PSR (temp);
-#endif
- }
- else
- {
- DPSImmRHS; /* TEQ immed */
- dest = LHS ^ rhs;
- ARMul_NegZero (state, dest);
- }
- break;
-
- case 0x34: /* CMP immed */
- UNDEF_Test;
- break;
-
- case 0x35: /* CMPP immed */
- if (DESTReg == 15)
- { /* CMPP immed */
-#ifdef MODE32
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
-#else
- temp = LHS - DPImmRHS;
- SETR15PSR (temp);
-#endif
- break;
- }
- else
- {
- lhs = LHS; /* CMP immed */
- rhs = DPImmRHS;
- dest = lhs - rhs;
- ARMul_NegZero (state, dest);
- if ((lhs >= rhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, lhs, rhs, dest);
- ARMul_SubOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- }
- break;
-
- case 0x36: /* CMN immed and MSR immed to SPSR */
- if (DESTReg == 15) /* MSR */
- ARMul_FixSPSR (state, instr, DPImmRHS);
- else
- {
- UNDEF_Test;
- }
- break;
-
- case 0x37: /* CMNP immed */
- if (DESTReg == 15)
- { /* CMNP immed */
-#ifdef MODE32
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
-#else
- temp = LHS + DPImmRHS;
- SETR15PSR (temp);
-#endif
- break;
- }
- else
- {
- lhs = LHS; /* CMN immed */
- rhs = DPImmRHS;
- dest = lhs + rhs;
- ASSIGNZ (dest == 0);
- if ((lhs | rhs) >> 30)
- { /* possible C,V,N to set */
- ASSIGNN (NEG (dest));
- ARMul_AddCarry (state, lhs, rhs, dest);
- ARMul_AddOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARN;
- CLEARC;
- CLEARV;
- }
- }
- break;
-
- case 0x38: /* ORR immed */
- dest = LHS | DPImmRHS;
- WRITEDEST (dest);
- break;
-
- case 0x39: /* ORRS immed */
- DPSImmRHS;
- dest = LHS | rhs;
- WRITESDEST (dest);
- break;
-
- case 0x3a: /* MOV immed */
- dest = DPImmRHS;
- WRITEDEST (dest);
- break;
-
- case 0x3b: /* MOVS immed */
- DPSImmRHS;
- WRITESDEST (rhs);
- break;
-
- case 0x3c: /* BIC immed */
- dest = LHS & ~DPImmRHS;
- WRITEDEST (dest);
- break;
-
- case 0x3d: /* BICS immed */
- DPSImmRHS;
- dest = LHS & ~rhs;
- WRITESDEST (dest);
- break;
-
- case 0x3e: /* MVN immed */
- dest = ~DPImmRHS;
- WRITEDEST (dest);
- break;
-
- case 0x3f: /* MVNS immed */
- DPSImmRHS;
- WRITESDEST (~rhs);
- break;
-
- /* Single Data Transfer Immediate RHS Instructions. */
-
- case 0x40: /* Store Word, No WriteBack, Post Dec, Immed */
- lhs = LHS;
- if (StoreWord (state, instr, lhs))
- LSBase = lhs - LSImmRHS;
- break;
-
- case 0x41: /* Load Word, No WriteBack, Post Dec, Immed */
- lhs = LHS;
- if (LoadWord (state, instr, lhs))
- LSBase = lhs - LSImmRHS;
- break;
-
- case 0x42: /* Store Word, WriteBack, Post Dec, Immed */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- lhs = LHS;
- temp = lhs - LSImmRHS;
- state->NtransSig = LOW;
- if (StoreWord (state, instr, lhs))
- LSBase = temp;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x43: /* Load Word, WriteBack, Post Dec, Immed */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (LoadWord (state, instr, lhs))
- LSBase = lhs - LSImmRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x44: /* Store Byte, No WriteBack, Post Dec, Immed */
- lhs = LHS;
- if (StoreByte (state, instr, lhs))
- LSBase = lhs - LSImmRHS;
- break;
-
- case 0x45: /* Load Byte, No WriteBack, Post Dec, Immed */
- lhs = LHS;
- if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = lhs - LSImmRHS;
- break;
-
- case 0x46: /* Store Byte, WriteBack, Post Dec, Immed */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (StoreByte (state, instr, lhs))
- LSBase = lhs - LSImmRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x47: /* Load Byte, WriteBack, Post Dec, Immed */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = lhs - LSImmRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x48: /* Store Word, No WriteBack, Post Inc, Immed */
- lhs = LHS;
- if (StoreWord (state, instr, lhs))
- LSBase = lhs + LSImmRHS;
- break;
-
- case 0x49: /* Load Word, No WriteBack, Post Inc, Immed */
- lhs = LHS;
- if (LoadWord (state, instr, lhs))
- LSBase = lhs + LSImmRHS;
- break;
-
- case 0x4a: /* Store Word, WriteBack, Post Inc, Immed */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (StoreWord (state, instr, lhs))
- LSBase = lhs + LSImmRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x4b: /* Load Word, WriteBack, Post Inc, Immed */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (LoadWord (state, instr, lhs))
- LSBase = lhs + LSImmRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x4c: /* Store Byte, No WriteBack, Post Inc, Immed */
- lhs = LHS;
- if (StoreByte (state, instr, lhs))
- LSBase = lhs + LSImmRHS;
- break;
-
- case 0x4d: /* Load Byte, No WriteBack, Post Inc, Immed */
- lhs = LHS;
- if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = lhs + LSImmRHS;
- break;
-
- case 0x4e: /* Store Byte, WriteBack, Post Inc, Immed */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (StoreByte (state, instr, lhs))
- LSBase = lhs + LSImmRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x4f: /* Load Byte, WriteBack, Post Inc, Immed */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = lhs + LSImmRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
-
- case 0x50: /* Store Word, No WriteBack, Pre Dec, Immed */
- (void) StoreWord (state, instr, LHS - LSImmRHS);
- break;
-
- case 0x51: /* Load Word, No WriteBack, Pre Dec, Immed */
- (void) LoadWord (state, instr, LHS - LSImmRHS);
- break;
-
- case 0x52: /* Store Word, WriteBack, Pre Dec, Immed */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- temp = LHS - LSImmRHS;
- if (StoreWord (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x53: /* Load Word, WriteBack, Pre Dec, Immed */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- temp = LHS - LSImmRHS;
- if (LoadWord (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x54: /* Store Byte, No WriteBack, Pre Dec, Immed */
- (void) StoreByte (state, instr, LHS - LSImmRHS);
- break;
-
- case 0x55: /* Load Byte, No WriteBack, Pre Dec, Immed */
- (void) LoadByte (state, instr, LHS - LSImmRHS, LUNSIGNED);
- break;
-
- case 0x56: /* Store Byte, WriteBack, Pre Dec, Immed */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- temp = LHS - LSImmRHS;
- if (StoreByte (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x57: /* Load Byte, WriteBack, Pre Dec, Immed */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- temp = LHS - LSImmRHS;
- if (LoadByte (state, instr, temp, LUNSIGNED))
- LSBase = temp;
- break;
-
- case 0x58: /* Store Word, No WriteBack, Pre Inc, Immed */
- (void) StoreWord (state, instr, LHS + LSImmRHS);
- break;
-
- case 0x59: /* Load Word, No WriteBack, Pre Inc, Immed */
- (void) LoadWord (state, instr, LHS + LSImmRHS);
- break;
-
- case 0x5a: /* Store Word, WriteBack, Pre Inc, Immed */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- temp = LHS + LSImmRHS;
- if (StoreWord (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x5b: /* Load Word, WriteBack, Pre Inc, Immed */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- temp = LHS + LSImmRHS;
- if (LoadWord (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x5c: /* Store Byte, No WriteBack, Pre Inc, Immed */
- (void) StoreByte (state, instr, LHS + LSImmRHS);
- break;
-
- case 0x5d: /* Load Byte, No WriteBack, Pre Inc, Immed */
- (void) LoadByte (state, instr, LHS + LSImmRHS, LUNSIGNED);
- break;
-
- case 0x5e: /* Store Byte, WriteBack, Pre Inc, Immed */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- temp = LHS + LSImmRHS;
- if (StoreByte (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x5f: /* Load Byte, WriteBack, Pre Inc, Immed */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- temp = LHS + LSImmRHS;
- if (LoadByte (state, instr, temp, LUNSIGNED))
- LSBase = temp;
- break;
-
-
- /* Single Data Transfer Register RHS Instructions. */
-
- case 0x60: /* Store Word, No WriteBack, Post Dec, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- if (StoreWord (state, instr, lhs))
- LSBase = lhs - LSRegRHS;
- break;
-
- case 0x61: /* Load Word, No WriteBack, Post Dec, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- temp = lhs - LSRegRHS;
- if (LoadWord (state, instr, lhs))
- LSBase = temp;
- break;
-
- case 0x62: /* Store Word, WriteBack, Post Dec, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (StoreWord (state, instr, lhs))
- LSBase = lhs - LSRegRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x63: /* Load Word, WriteBack, Post Dec, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- temp = lhs - LSRegRHS;
- state->NtransSig = LOW;
- if (LoadWord (state, instr, lhs))
- LSBase = temp;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x64: /* Store Byte, No WriteBack, Post Dec, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- if (StoreByte (state, instr, lhs))
- LSBase = lhs - LSRegRHS;
- break;
-
- case 0x65: /* Load Byte, No WriteBack, Post Dec, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- temp = lhs - LSRegRHS;
- if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = temp;
- break;
-
- case 0x66: /* Store Byte, WriteBack, Post Dec, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (StoreByte (state, instr, lhs))
- LSBase = lhs - LSRegRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x67: /* Load Byte, WriteBack, Post Dec, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- temp = lhs - LSRegRHS;
- state->NtransSig = LOW;
- if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = temp;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x68: /* Store Word, No WriteBack, Post Inc, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- if (StoreWord (state, instr, lhs))
- LSBase = lhs + LSRegRHS;
- break;
-
- case 0x69: /* Load Word, No WriteBack, Post Inc, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- temp = lhs + LSRegRHS;
- if (LoadWord (state, instr, lhs))
- LSBase = temp;
- break;
-
- case 0x6a: /* Store Word, WriteBack, Post Inc, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (StoreWord (state, instr, lhs))
- LSBase = lhs + LSRegRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x6b: /* Load Word, WriteBack, Post Inc, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- temp = lhs + LSRegRHS;
- state->NtransSig = LOW;
- if (LoadWord (state, instr, lhs))
- LSBase = temp;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x6c: /* Store Byte, No WriteBack, Post Inc, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- if (StoreByte (state, instr, lhs))
- LSBase = lhs + LSRegRHS;
- break;
-
- case 0x6d: /* Load Byte, No WriteBack, Post Inc, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- temp = lhs + LSRegRHS;
- if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = temp;
- break;
-
- case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (StoreByte (state, instr, lhs))
- LSBase = lhs + LSRegRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x6f: /* Load Byte, WriteBack, Post Inc, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- temp = lhs + LSRegRHS;
- state->NtransSig = LOW;
- if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = temp;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
-
- case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- (void) StoreWord (state, instr, LHS - LSRegRHS);
- break;
-
- case 0x71: /* Load Word, No WriteBack, Pre Dec, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- (void) LoadWord (state, instr, LHS - LSRegRHS);
- break;
-
- case 0x72: /* Store Word, WriteBack, Pre Dec, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- temp = LHS - LSRegRHS;
- if (StoreWord (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x73: /* Load Word, WriteBack, Pre Dec, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- temp = LHS - LSRegRHS;
- if (LoadWord (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x74: /* Store Byte, No WriteBack, Pre Dec, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- (void) StoreByte (state, instr, LHS - LSRegRHS);
- break;
-
- case 0x75: /* Load Byte, No WriteBack, Pre Dec, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- (void) LoadByte (state, instr, LHS - LSRegRHS, LUNSIGNED);
- break;
-
- case 0x76: /* Store Byte, WriteBack, Pre Dec, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- temp = LHS - LSRegRHS;
- if (StoreByte (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x77: /* Load Byte, WriteBack, Pre Dec, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- temp = LHS - LSRegRHS;
- if (LoadByte (state, instr, temp, LUNSIGNED))
- LSBase = temp;
- break;
-
- case 0x78: /* Store Word, No WriteBack, Pre Inc, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- (void) StoreWord (state, instr, LHS + LSRegRHS);
- break;
-
- case 0x79: /* Load Word, No WriteBack, Pre Inc, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- (void) LoadWord (state, instr, LHS + LSRegRHS);
- break;
-
- case 0x7a: /* Store Word, WriteBack, Pre Inc, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- temp = LHS + LSRegRHS;
- if (StoreWord (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x7b: /* Load Word, WriteBack, Pre Inc, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- temp = LHS + LSRegRHS;
- if (LoadWord (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x7c: /* Store Byte, No WriteBack, Pre Inc, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- (void) StoreByte (state, instr, LHS + LSRegRHS);
- break;
-
- case 0x7d: /* Load Byte, No WriteBack, Pre Inc, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- (void) LoadByte (state, instr, LHS + LSRegRHS, LUNSIGNED);
- break;
-
- case 0x7e: /* Store Byte, WriteBack, Pre Inc, Reg */
- if (BIT (4))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- temp = LHS + LSRegRHS;
- if (StoreByte (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x7f: /* Load Byte, WriteBack, Pre Inc, Reg */
- if (BIT (4))
- {
- /* Check for the special breakpoint opcode.
- This value should correspond to the value defined
- as ARM_BE_BREAKPOINT in gdb/arm/tm-arm.h. */
- if (BITS (0, 19) == 0xfdefe)
- {
- if (!ARMul_OSHandleSWI (state, SWI_Breakpoint))
- ARMul_Abort (state, ARMul_SWIV);
- }
- else
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- temp = LHS + LSRegRHS;
- if (LoadByte (state, instr, temp, LUNSIGNED))
- LSBase = temp;
- break;
-
-
- /* Multiple Data Transfer Instructions. */
-
- case 0x80: /* Store, No WriteBack, Post Dec */
- STOREMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
- break;
-
- case 0x81: /* Load, No WriteBack, Post Dec */
- LOADMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
- break;
-
- case 0x82: /* Store, WriteBack, Post Dec */
- temp = LSBase - LSMNumRegs;
- STOREMULT (instr, temp + 4L, temp);
- break;
-
- case 0x83: /* Load, WriteBack, Post Dec */
- temp = LSBase - LSMNumRegs;
- LOADMULT (instr, temp + 4L, temp);
- break;
-
- case 0x84: /* Store, Flags, No WriteBack, Post Dec */
- STORESMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
- break;
-
- case 0x85: /* Load, Flags, No WriteBack, Post Dec */
- LOADSMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
- break;
-
- case 0x86: /* Store, Flags, WriteBack, Post Dec */
- temp = LSBase - LSMNumRegs;
- STORESMULT (instr, temp + 4L, temp);
- break;
-
- case 0x87: /* Load, Flags, WriteBack, Post Dec */
- temp = LSBase - LSMNumRegs;
- LOADSMULT (instr, temp + 4L, temp);
- break;
-
- case 0x88: /* Store, No WriteBack, Post Inc */
- STOREMULT (instr, LSBase, 0L);
- break;
-
- case 0x89: /* Load, No WriteBack, Post Inc */
- LOADMULT (instr, LSBase, 0L);
- break;
-
- case 0x8a: /* Store, WriteBack, Post Inc */
- temp = LSBase;
- STOREMULT (instr, temp, temp + LSMNumRegs);
- break;
-
- case 0x8b: /* Load, WriteBack, Post Inc */
- temp = LSBase;
- LOADMULT (instr, temp, temp + LSMNumRegs);
- break;
-
- case 0x8c: /* Store, Flags, No WriteBack, Post Inc */
- STORESMULT (instr, LSBase, 0L);
- break;
-
- case 0x8d: /* Load, Flags, No WriteBack, Post Inc */
- LOADSMULT (instr, LSBase, 0L);
- break;
-
- case 0x8e: /* Store, Flags, WriteBack, Post Inc */
- temp = LSBase;
- STORESMULT (instr, temp, temp + LSMNumRegs);
- break;
-
- case 0x8f: /* Load, Flags, WriteBack, Post Inc */
- temp = LSBase;
- LOADSMULT (instr, temp, temp + LSMNumRegs);
- break;
-
- case 0x90: /* Store, No WriteBack, Pre Dec */
- STOREMULT (instr, LSBase - LSMNumRegs, 0L);
- break;
-
- case 0x91: /* Load, No WriteBack, Pre Dec */
- LOADMULT (instr, LSBase - LSMNumRegs, 0L);
- break;
-
- case 0x92: /* Store, WriteBack, Pre Dec */
- temp = LSBase - LSMNumRegs;
- STOREMULT (instr, temp, temp);
- break;
-
- case 0x93: /* Load, WriteBack, Pre Dec */
- temp = LSBase - LSMNumRegs;
- LOADMULT (instr, temp, temp);
- break;
-
- case 0x94: /* Store, Flags, No WriteBack, Pre Dec */
- STORESMULT (instr, LSBase - LSMNumRegs, 0L);
- break;
-
- case 0x95: /* Load, Flags, No WriteBack, Pre Dec */
- LOADSMULT (instr, LSBase - LSMNumRegs, 0L);
- break;
-
- case 0x96: /* Store, Flags, WriteBack, Pre Dec */
- temp = LSBase - LSMNumRegs;
- STORESMULT (instr, temp, temp);
- break;
-
- case 0x97: /* Load, Flags, WriteBack, Pre Dec */
- temp = LSBase - LSMNumRegs;
- LOADSMULT (instr, temp, temp);
- break;
-
- case 0x98: /* Store, No WriteBack, Pre Inc */
- STOREMULT (instr, LSBase + 4L, 0L);
- break;
-
- case 0x99: /* Load, No WriteBack, Pre Inc */
- LOADMULT (instr, LSBase + 4L, 0L);
- break;
-
- case 0x9a: /* Store, WriteBack, Pre Inc */
- temp = LSBase;
- STOREMULT (instr, temp + 4L, temp + LSMNumRegs);
- break;
-
- case 0x9b: /* Load, WriteBack, Pre Inc */
- temp = LSBase;
- LOADMULT (instr, temp + 4L, temp + LSMNumRegs);
- break;
-
- case 0x9c: /* Store, Flags, No WriteBack, Pre Inc */
- STORESMULT (instr, LSBase + 4L, 0L);
- break;
-
- case 0x9d: /* Load, Flags, No WriteBack, Pre Inc */
- LOADSMULT (instr, LSBase + 4L, 0L);
- break;
-
- case 0x9e: /* Store, Flags, WriteBack, Pre Inc */
- temp = LSBase;
- STORESMULT (instr, temp + 4L, temp + LSMNumRegs);
- break;
-
- case 0x9f: /* Load, Flags, WriteBack, Pre Inc */
- temp = LSBase;
- LOADSMULT (instr, temp + 4L, temp + LSMNumRegs);
- break;
-
-
- /* Branch forward. */
- case 0xa0:
- case 0xa1:
- case 0xa2:
- case 0xa3:
- case 0xa4:
- case 0xa5:
- case 0xa6:
- case 0xa7:
- state->Reg[15] = pc + 8 + POSBRANCH;
- FLUSHPIPE;
- break;
-
-
- /* Branch backward. */
- case 0xa8:
- case 0xa9:
- case 0xaa:
- case 0xab:
- case 0xac:
- case 0xad:
- case 0xae:
- case 0xaf:
- state->Reg[15] = pc + 8 + NEGBRANCH;
- FLUSHPIPE;
- break;
-
-
- /* Branch and Link forward. */
- case 0xb0:
- case 0xb1:
- case 0xb2:
- case 0xb3:
- case 0xb4:
- case 0xb5:
- case 0xb6:
- case 0xb7:
- /* Put PC into Link. */
-#ifdef MODE32
- state->Reg[14] = pc + 4;
-#else
- state->Reg[14] = (pc + 4) | ECC | ER15INT | EMODE;
-#endif
- state->Reg[15] = pc + 8 + POSBRANCH;
- FLUSHPIPE;
- break;
-
-
- /* Branch and Link backward. */
- case 0xb8:
- case 0xb9:
- case 0xba:
- case 0xbb:
- case 0xbc:
- case 0xbd:
- case 0xbe:
- case 0xbf:
- /* Put PC into Link. */
-#ifdef MODE32
- state->Reg[14] = pc + 4;
-#else
- state->Reg[14] = (pc + 4) | ECC | ER15INT | EMODE;
-#endif
- state->Reg[15] = pc + 8 + NEGBRANCH;
- FLUSHPIPE;
- break;
-
- /* Co-Processor Data Transfers. */
- case 0xc4:
- if (state->is_v5)
- {
- /* Reading from R15 is UNPREDICTABLE. */
- if (BITS (12, 15) == 15 || BITS (16, 19) == 15)
- ARMul_UndefInstr (state, instr);
- /* Is access to coprocessor 0 allowed ? */
- else if (! CP_ACCESS_ALLOWED (state, CPNum))
- ARMul_UndefInstr (state, instr);
- /* Special treatment for XScale coprocessors. */
- else if (state->is_XScale)
- {
- /* Only opcode 0 is supported. */
- if (BITS (4, 7) != 0x00)
- ARMul_UndefInstr (state, instr);
- /* Only coporcessor 0 is supported. */
- else if (CPNum != 0x00)
- ARMul_UndefInstr (state, instr);
- /* Only accumulator 0 is supported. */
- else if (BITS (0, 3) != 0x00)
- ARMul_UndefInstr (state, instr);
- else
- {
- /* XScale MAR insn. Move two registers into accumulator. */
- state->Accumulator = state->Reg[BITS (12, 15)];
- state->Accumulator += (ARMdword) state->Reg[BITS (16, 19)] << 32;
- }
- }
- else
- /* FIXME: Not sure what to do for other v5 processors. */
- ARMul_UndefInstr (state, instr);
- break;
- }
- /* Drop through. */
-
- case 0xc0: /* Store , No WriteBack , Post Dec */
- ARMul_STC (state, instr, LHS);
- break;
-
- case 0xc5:
- if (state->is_v5)
- {
- /* Writes to R15 are UNPREDICATABLE. */
- if (DESTReg == 15 || LHSReg == 15)
- ARMul_UndefInstr (state, instr);
- /* Is access to the coprocessor allowed ? */
- else if (! CP_ACCESS_ALLOWED (state, CPNum))
- ARMul_UndefInstr (state, instr);
- /* Special handling for XScale coprcoessors. */
- else if (state->is_XScale)
- {
- /* Only opcode 0 is supported. */
- if (BITS (4, 7) != 0x00)
- ARMul_UndefInstr (state, instr);
- /* Only coprocessor 0 is supported. */
- else if (CPNum != 0x00)
- ARMul_UndefInstr (state, instr);
- /* Only accumulator 0 is supported. */
- else if (BITS (0, 3) != 0x00)
- ARMul_UndefInstr (state, instr);
- else
- {
- /* XScale MRA insn. Move accumulator into two registers. */
- ARMword t1 = (state->Accumulator >> 32) & 255;
-
- if (t1 & 128)
- t1 -= 256;
-
- state->Reg[BITS (12, 15)] = state->Accumulator;
- state->Reg[BITS (16, 19)] = t1;
- break;
- }
- }
- else
- /* FIXME: Not sure what to do for other v5 processors. */
- ARMul_UndefInstr (state, instr);
- break;
- }
- /* Drop through. */
-
- case 0xc1: /* Load , No WriteBack , Post Dec */
- ARMul_LDC (state, instr, LHS);
- break;
-
- case 0xc2:
- case 0xc6: /* Store , WriteBack , Post Dec */
- lhs = LHS;
- state->Base = lhs - LSCOff;
- ARMul_STC (state, instr, lhs);
- break;
-
- case 0xc3:
- case 0xc7: /* Load , WriteBack , Post Dec */
- lhs = LHS;
- state->Base = lhs - LSCOff;
- ARMul_LDC (state, instr, lhs);
- break;
-
- case 0xc8:
- case 0xcc: /* Store , No WriteBack , Post Inc */
- ARMul_STC (state, instr, LHS);
- break;
-
- case 0xc9:
- case 0xcd: /* Load , No WriteBack , Post Inc */
- ARMul_LDC (state, instr, LHS);
- break;
-
- case 0xca:
- case 0xce: /* Store , WriteBack , Post Inc */
- lhs = LHS;
- state->Base = lhs + LSCOff;
- ARMul_STC (state, instr, LHS);
- break;
-
- case 0xcb:
- case 0xcf: /* Load , WriteBack , Post Inc */
- lhs = LHS;
- state->Base = lhs + LSCOff;
- ARMul_LDC (state, instr, LHS);
- break;
-
- case 0xd0:
- case 0xd4: /* Store , No WriteBack , Pre Dec */
- ARMul_STC (state, instr, LHS - LSCOff);
- break;
-
- case 0xd1:
- case 0xd5: /* Load , No WriteBack , Pre Dec */
- ARMul_LDC (state, instr, LHS - LSCOff);
- break;
-
- case 0xd2:
- case 0xd6: /* Store , WriteBack , Pre Dec */
- lhs = LHS - LSCOff;
- state->Base = lhs;
- ARMul_STC (state, instr, lhs);
- break;
-
- case 0xd3:
- case 0xd7: /* Load , WriteBack , Pre Dec */
- lhs = LHS - LSCOff;
- state->Base = lhs;
- ARMul_LDC (state, instr, lhs);
- break;
-
- case 0xd8:
- case 0xdc: /* Store , No WriteBack , Pre Inc */
- ARMul_STC (state, instr, LHS + LSCOff);
- break;
-
- case 0xd9:
- case 0xdd: /* Load , No WriteBack , Pre Inc */
- ARMul_LDC (state, instr, LHS + LSCOff);
- break;
-
- case 0xda:
- case 0xde: /* Store , WriteBack , Pre Inc */
- lhs = LHS + LSCOff;
- state->Base = lhs;
- ARMul_STC (state, instr, lhs);
- break;
-
- case 0xdb:
- case 0xdf: /* Load , WriteBack , Pre Inc */
- lhs = LHS + LSCOff;
- state->Base = lhs;
- ARMul_LDC (state, instr, lhs);
- break;
-
-
- /* Co-Processor Register Transfers (MCR) and Data Ops. */
- case 0xe2:
- if (! CP_ACCESS_ALLOWED (state, CPNum))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- if (state->is_XScale)
- switch (BITS (18, 19))
- {
- case 0x0:
- {
- /* XScale MIA instruction. Signed multiplication of two 32 bit
- values and addition to 40 bit accumulator. */
- long long Rm = state->Reg[MULLHSReg];
- long long Rs = state->Reg[MULACCReg];
-
- if (Rm & (1 << 31))
- Rm -= 1ULL << 32;
- if (Rs & (1 << 31))
- Rs -= 1ULL << 32;
- state->Accumulator += Rm * Rs;
- }
- goto donext;
-
- case 0x2:
- {
- /* XScale MIAPH instruction. */
- ARMword t1 = state->Reg[MULLHSReg] >> 16;
- ARMword t2 = state->Reg[MULACCReg] >> 16;
- ARMword t3 = state->Reg[MULLHSReg] & 0xffff;
- ARMword t4 = state->Reg[MULACCReg] & 0xffff;
- long long t5;
-
- if (t1 & (1 << 15))
- t1 -= 1 << 16;
- if (t2 & (1 << 15))
- t2 -= 1 << 16;
- if (t3 & (1 << 15))
- t3 -= 1 << 16;
- if (t4 & (1 << 15))
- t4 -= 1 << 16;
- t1 *= t2;
- t5 = t1;
- if (t5 & (1 << 31))
- t5 -= 1ULL << 32;
- state->Accumulator += t5;
- t3 *= t4;
- t5 = t3;
- if (t5 & (1 << 31))
- t5 -= 1ULL << 32;
- state->Accumulator += t5;
- }
- goto donext;
-
- case 0x3:
- {
- /* XScale MIAxy instruction. */
- ARMword t1;
- ARMword t2;
- long long t5;
-
- if (BIT (17))
- t1 = state->Reg[MULLHSReg] >> 16;
- else
- t1 = state->Reg[MULLHSReg] & 0xffff;
-
- if (BIT (16))
- t2 = state->Reg[MULACCReg] >> 16;
- else
- t2 = state->Reg[MULACCReg] & 0xffff;
-
- if (t1 & (1 << 15))
- t1 -= 1 << 16;
- if (t2 & (1 << 15))
- t2 -= 1 << 16;
- t1 *= t2;
- t5 = t1;
- if (t5 & (1 << 31))
- t5 -= 1ULL << 32;
- state->Accumulator += t5;
- }
- goto donext;
-
- default:
- break;
- }
- /* Drop through. */
-
- case 0xe0:
- case 0xe4:
- case 0xe6:
- case 0xe8:
- case 0xea:
- case 0xec:
- case 0xee:
- if (BIT (4))
- { /* MCR */
- if (DESTReg == 15)
- {
- UNDEF_MCRPC;
-#ifdef MODE32
- ARMul_MCR (state, instr, state->Reg[15] + isize);
-#else
- ARMul_MCR (state, instr, ECC | ER15INT | EMODE |
- ((state->Reg[15] + isize) & R15PCBITS));
-#endif
- }
- else
- ARMul_MCR (state, instr, DEST);
- }
- else /* CDP Part 1 */
- ARMul_CDP (state, instr);
- break;
-
-
- /* Co-Processor Register Transfers (MRC) and Data Ops. */
- case 0xe1:
- case 0xe3:
- case 0xe5:
- case 0xe7:
- case 0xe9:
- case 0xeb:
- case 0xed:
- case 0xef:
- if (BIT (4))
- { /* MRC */
- temp = ARMul_MRC (state, instr);
- if (DESTReg == 15)
- {
- ASSIGNN ((temp & NBIT) != 0);
- ASSIGNZ ((temp & ZBIT) != 0);
- ASSIGNC ((temp & CBIT) != 0);
- ASSIGNV ((temp & VBIT) != 0);
- }
- else
- DEST = temp;
- }
- else /* CDP Part 2 */
- ARMul_CDP (state, instr);
- break;
-
-
- /* SWI instruction. */
- case 0xf0:
- case 0xf1:
- case 0xf2:
- case 0xf3:
- case 0xf4:
- case 0xf5:
- case 0xf6:
- case 0xf7:
- case 0xf8:
- case 0xf9:
- case 0xfa:
- case 0xfb:
- case 0xfc:
- case 0xfd:
- case 0xfe:
- case 0xff:
- if (instr == ARMul_ABORTWORD && state->AbortAddr == pc)
- {
- /* A prefetch abort. */
- XScale_set_fsr_far (state, ARMul_CP15_R5_MMU_EXCPT, pc);
- ARMul_Abort (state, ARMul_PrefetchAbortV);
- break;
- }
-
- if (!ARMul_OSHandleSWI (state, BITS (0, 23)))
- ARMul_Abort (state, ARMul_SWIV);
-
- break;
- }
- }
-
-#ifdef MODET
- donext:
-#endif
-
-#ifdef NEED_UI_LOOP_HOOK
- if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0)
- {
- ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
- ui_loop_hook (0);
- }
-#endif /* NEED_UI_LOOP_HOOK */
-
- if (state->Emulate == ONCE)
- state->Emulate = STOP;
- /* If we have changed mode, allow the PC to advance before stopping. */
- else if (state->Emulate == CHANGEMODE)
- continue;
- else if (state->Emulate != RUN)
- break;
- }
- while (!stop_simulator);
-
- state->decoded = decoded;
- state->loaded = loaded;
- state->pc = pc;
-
- return pc;
-}
-
-/* This routine evaluates most Data Processing register RHS's with the S
- bit clear. It is intended to be called from the macro DPRegRHS, which
- filters the common case of an unshifted register with in line code. */
-
-static ARMword
-GetDPRegRHS (ARMul_State * state, ARMword instr)
-{
- ARMword shamt, base;
-
- base = RHSReg;
- if (BIT (4))
- {
- /* Shift amount in a register. */
- UNDEF_Shift;
- INCPC;
-#ifndef MODE32
- if (base == 15)
- base = ECC | ER15INT | R15PC | EMODE;
- else
-#endif
- base = state->Reg[base];
- ARMul_Icycles (state, 1, 0L);
- shamt = state->Reg[BITS (8, 11)] & 0xff;
- switch ((int) BITS (5, 6))
- {
- case LSL:
- if (shamt == 0)
- return (base);
- else if (shamt >= 32)
- return (0);
- else
- return (base << shamt);
- case LSR:
- if (shamt == 0)
- return (base);
- else if (shamt >= 32)
- return (0);
- else
- return (base >> shamt);
- case ASR:
- if (shamt == 0)
- return (base);
- else if (shamt >= 32)
- return ((ARMword) ((long int) base >> 31L));
- else
- return ((ARMword) ((long int) base >> (int) shamt));
- case ROR:
- shamt &= 0x1f;
- if (shamt == 0)
- return (base);
- else
- return ((base << (32 - shamt)) | (base >> shamt));
- }
- }
- else
- {
- /* Shift amount is a constant. */
-#ifndef MODE32
- if (base == 15)
- base = ECC | ER15INT | R15PC | EMODE;
- else
-#endif
- base = state->Reg[base];
- shamt = BITS (7, 11);
- switch ((int) BITS (5, 6))
- {
- case LSL:
- return (base << shamt);
- case LSR:
- if (shamt == 0)
- return (0);
- else
- return (base >> shamt);
- case ASR:
- if (shamt == 0)
- return ((ARMword) ((long int) base >> 31L));
- else
- return ((ARMword) ((long int) base >> (int) shamt));
- case ROR:
- if (shamt == 0) /* its an RRX */
- return ((base >> 1) | (CFLAG << 31));
- else
- return ((base << (32 - shamt)) | (base >> shamt));
- }
- }
-
- return 0;
-}
-
-/* This routine evaluates most Logical Data Processing register RHS's
- with the S bit set. It is intended to be called from the macro
- DPSRegRHS, which filters the common case of an unshifted register
- with in line code. */
-
-static ARMword
-GetDPSRegRHS (ARMul_State * state, ARMword instr)
-{
- ARMword shamt, base;
-
- base = RHSReg;
- if (BIT (4))
- {
- /* Shift amount in a register. */
- UNDEF_Shift;
- INCPC;
-#ifndef MODE32
- if (base == 15)
- base = ECC | ER15INT | R15PC | EMODE;
- else
-#endif
- base = state->Reg[base];
- ARMul_Icycles (state, 1, 0L);
- shamt = state->Reg[BITS (8, 11)] & 0xff;
- switch ((int) BITS (5, 6))
- {
- case LSL:
- if (shamt == 0)
- return (base);
- else if (shamt == 32)
- {
- ASSIGNC (base & 1);
- return (0);
- }
- else if (shamt > 32)
- {
- CLEARC;
- return (0);
- }
- else
- {
- ASSIGNC ((base >> (32 - shamt)) & 1);
- return (base << shamt);
- }
- case LSR:
- if (shamt == 0)
- return (base);
- else if (shamt == 32)
- {
- ASSIGNC (base >> 31);
- return (0);
- }
- else if (shamt > 32)
- {
- CLEARC;
- return (0);
- }
- else
- {
- ASSIGNC ((base >> (shamt - 1)) & 1);
- return (base >> shamt);
- }
- case ASR:
- if (shamt == 0)
- return (base);
- else if (shamt >= 32)
- {
- ASSIGNC (base >> 31L);
- return ((ARMword) ((long int) base >> 31L));
- }
- else
- {
- ASSIGNC ((ARMword) ((long int) base >> (int) (shamt - 1)) & 1);
- return ((ARMword) ((long int) base >> (int) shamt));
- }
- case ROR:
- if (shamt == 0)
- return (base);
- shamt &= 0x1f;
- if (shamt == 0)
- {
- ASSIGNC (base >> 31);
- return (base);
- }
- else
- {
- ASSIGNC ((base >> (shamt - 1)) & 1);
- return ((base << (32 - shamt)) | (base >> shamt));
- }
- }
- }
- else
- {
- /* Shift amount is a constant. */
-#ifndef MODE32
- if (base == 15)
- base = ECC | ER15INT | R15PC | EMODE;
- else
-#endif
- base = state->Reg[base];
- shamt = BITS (7, 11);
- switch ((int) BITS (5, 6))
- {
- case LSL:
- ASSIGNC ((base >> (32 - shamt)) & 1);
- return (base << shamt);
- case LSR:
- if (shamt == 0)
- {
- ASSIGNC (base >> 31);
- return (0);
- }
- else
- {
- ASSIGNC ((base >> (shamt - 1)) & 1);
- return (base >> shamt);
- }
- case ASR:
- if (shamt == 0)
- {
- ASSIGNC (base >> 31L);
- return ((ARMword) ((long int) base >> 31L));
- }
- else
- {
- ASSIGNC ((ARMword) ((long int) base >> (int) (shamt - 1)) & 1);
- return ((ARMword) ((long int) base >> (int) shamt));
- }
- case ROR:
- if (shamt == 0)
- { /* its an RRX */
- shamt = CFLAG;
- ASSIGNC (base & 1);
- return ((base >> 1) | (shamt << 31));
- }
- else
- {
- ASSIGNC ((base >> (shamt - 1)) & 1);
- return ((base << (32 - shamt)) | (base >> shamt));
- }
- }
- }
-
- return 0;
-}
-
-/* This routine handles writes to register 15 when the S bit is not set. */
-
-static void
-WriteR15 (ARMul_State * state, ARMword src)
-{
- /* The ARM documentation states that the two least significant bits
- are discarded when setting PC, except in the cases handled by
- WriteR15Branch() below. It's probably an oversight: in THUMB
- mode, the second least significant bit should probably not be
- discarded. */
-#ifdef MODET
- if (TFLAG)
- src &= 0xfffffffe;
- else
-#endif
- src &= 0xfffffffc;
-#ifdef MODE32
- state->Reg[15] = src & PCBITS;
-#else
- state->Reg[15] = (src & R15PCBITS) | ECC | ER15INT | EMODE;
- ARMul_R15Altered (state);
-#endif
- FLUSHPIPE;
-}
-
-/* This routine handles writes to register 15 when the S bit is set. */
-
-static void
-WriteSR15 (ARMul_State * state, ARMword src)
-{
-#ifdef MODE32
- if (state->Bank > 0)
- {
- state->Cpsr = state->Spsr[state->Bank];
- ARMul_CPSRAltered (state);
- }
-#ifdef MODET
- if (TFLAG)
- src &= 0xfffffffe;
- else
-#endif
- src &= 0xfffffffc;
- state->Reg[15] = src & PCBITS;
-#else
-#ifdef MODET
- if (TFLAG)
- abort (); /* ARMul_R15Altered would have to support it. */
- else
-#endif
- src &= 0xfffffffc;
- if (state->Bank == USERBANK)
- state->Reg[15] = (src & (CCBITS | R15PCBITS)) | ER15INT | EMODE;
- else
- state->Reg[15] = src;
- ARMul_R15Altered (state);
-#endif
- FLUSHPIPE;
-}
-
-/* In machines capable of running in Thumb mode, BX, BLX, LDR and LDM
- will switch to Thumb mode if the least significant bit is set. */
-
-static void
-WriteR15Branch (ARMul_State * state, ARMword src)
-{
-#ifdef MODET
- if (src & 1)
- {
- /* Thumb bit. */
- SETT;
- state->Reg[15] = src & 0xfffffffe;
- }
- else
- {
- CLEART;
- state->Reg[15] = src & 0xfffffffc;
- }
- FLUSHPIPE;
-#else
- WriteR15 (state, src);
-#endif
-}
-
-/* This routine evaluates most Load and Store register RHS's. It is
- intended to be called from the macro LSRegRHS, which filters the
- common case of an unshifted register with in line code. */
-
-static ARMword
-GetLSRegRHS (ARMul_State * state, ARMword instr)
-{
- ARMword shamt, base;
-
- base = RHSReg;
-#ifndef MODE32
- if (base == 15)
- base = ECC | ER15INT | R15PC | EMODE; /* Now forbidden, but .... */
- else
-#endif
- base = state->Reg[base];
-
- shamt = BITS (7, 11);
- switch ((int) BITS (5, 6))
- {
- case LSL:
- return (base << shamt);
- case LSR:
- if (shamt == 0)
- return (0);
- else
- return (base >> shamt);
- case ASR:
- if (shamt == 0)
- return ((ARMword) ((long int) base >> 31L));
- else
- return ((ARMword) ((long int) base >> (int) shamt));
- case ROR:
- if (shamt == 0) /* its an RRX */
- return ((base >> 1) | (CFLAG << 31));
- else
- return ((base << (32 - shamt)) | (base >> shamt));
- default:
- break;
- }
- return 0;
-}
-
-/* This routine evaluates the ARM7T halfword and signed transfer RHS's. */
-
-static ARMword
-GetLS7RHS (ARMul_State * state, ARMword instr)
-{
- if (BIT (22) == 0)
- {
- /* Register. */
-#ifndef MODE32
- if (RHSReg == 15)
- return ECC | ER15INT | R15PC | EMODE; /* Now forbidden, but ... */
-#endif
- return state->Reg[RHSReg];
- }
-
- /* Otherwise an immediate. */
- return BITS (0, 3) | (BITS (8, 11) << 4);
-}
-
-/* This function does the work of loading a word for a LDR instruction. */
-
-static unsigned
-LoadWord (ARMul_State * state, ARMword instr, ARMword address)
-{
- ARMword dest;
-
- BUSUSEDINCPCS;
-#ifndef MODE32
- if (ADDREXCEPT (address))
- INTERNALABORT (address);
-#endif
-
- dest = ARMul_LoadWordN (state, address);
-
- if (state->Aborted)
- {
- TAKEABORT;
- return (state->lateabtSig);
- }
- if (address & 3)
- dest = ARMul_Align (state, address, dest);
- WRITEDESTB (dest);
- ARMul_Icycles (state, 1, 0L);
-
- return (DESTReg != LHSReg);
-}
-
-#ifdef MODET
-/* This function does the work of loading a halfword. */
-
-static unsigned
-LoadHalfWord (ARMul_State * state, ARMword instr, ARMword address,
- int signextend)
-{
- ARMword dest;
-
- BUSUSEDINCPCS;
-#ifndef MODE32
- if (ADDREXCEPT (address))
- {
- INTERNALABORT (address);
- }
-#endif
- dest = ARMul_LoadHalfWord (state, address);
- if (state->Aborted)
- {
- TAKEABORT;
- return (state->lateabtSig);
- }
- UNDEF_LSRBPC;
- if (signextend)
- {
- if (dest & 1 << (16 - 1))
- dest = (dest & ((1 << 16) - 1)) - (1 << 16);
- }
- WRITEDEST (dest);
- ARMul_Icycles (state, 1, 0L);
- return (DESTReg != LHSReg);
-}
-
-#endif /* MODET */
-
-/* This function does the work of loading a byte for a LDRB instruction. */
-
-static unsigned
-LoadByte (ARMul_State * state, ARMword instr, ARMword address, int signextend)
-{
- ARMword dest;
-
- BUSUSEDINCPCS;
-#ifndef MODE32
- if (ADDREXCEPT (address))
- {
- INTERNALABORT (address);
- }
-#endif
- dest = ARMul_LoadByte (state, address);
- if (state->Aborted)
- {
- TAKEABORT;
- return (state->lateabtSig);
- }
- UNDEF_LSRBPC;
- if (signextend)
- {
- if (dest & 1 << (8 - 1))
- dest = (dest & ((1 << 8) - 1)) - (1 << 8);
- }
- WRITEDEST (dest);
- ARMul_Icycles (state, 1, 0L);
- return (DESTReg != LHSReg);
-}
-
-/* This function does the work of loading two words for a LDRD instruction. */
-
-static void
-Handle_Load_Double (ARMul_State * state, ARMword instr)
-{
- ARMword dest_reg;
- ARMword addr_reg;
- ARMword write_back = BIT (21);
- ARMword immediate = BIT (22);
- ARMword add_to_base = BIT (23);
- ARMword pre_indexed = BIT (24);
- ARMword offset;
- ARMword addr;
- ARMword sum;
- ARMword base;
- ARMword value1;
- ARMword value2;
-
- BUSUSEDINCPCS;
-
- /* If the writeback bit is set, the pre-index bit must be clear. */
- if (write_back && ! pre_indexed)
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- /* Extract the base address register. */
- addr_reg = LHSReg;
-
- /* Extract the destination register and check it. */
- dest_reg = DESTReg;
-
- /* Destination register must be even. */
- if ((dest_reg & 1)
- /* Destination register cannot be LR. */
- || (dest_reg == 14))
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- /* Compute the base address. */
- base = state->Reg[addr_reg];
-
- /* Compute the offset. */
- offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state->Reg[RHSReg];
-
- /* Compute the sum of the two. */
- if (add_to_base)
- sum = base + offset;
- else
- sum = base - offset;
-
- /* If this is a pre-indexed mode use the sum. */
- if (pre_indexed)
- addr = sum;
- else
- addr = base;
-
- /* The address must be aligned on a 8 byte boundary. */
- if (addr & 0x7)
- {
-#ifdef ABORTS
- ARMul_DATAABORT (addr);
-#else
- ARMul_UndefInstr (state, instr);
-#endif
- return;
- }
-
- /* For pre indexed or post indexed addressing modes,
- check that the destination registers do not overlap
- the address registers. */
- if ((! pre_indexed || write_back)
- && ( addr_reg == dest_reg
- || addr_reg == dest_reg + 1))
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- /* Load the words. */
- value1 = ARMul_LoadWordN (state, addr);
- value2 = ARMul_LoadWordN (state, addr + 4);
-
- /* Check for data aborts. */
- if (state->Aborted)
- {
- TAKEABORT;
- return;
- }
-
- ARMul_Icycles (state, 2, 0L);
-
- /* Store the values. */
- state->Reg[dest_reg] = value1;
- state->Reg[dest_reg + 1] = value2;
-
- /* Do the post addressing and writeback. */
- if (! pre_indexed)
- addr = sum;
-
- if (! pre_indexed || write_back)
- state->Reg[addr_reg] = addr;
-}
-
-/* This function does the work of storing two words for a STRD instruction. */
-
-static void
-Handle_Store_Double (ARMul_State * state, ARMword instr)
-{
- ARMword src_reg;
- ARMword addr_reg;
- ARMword write_back = BIT (21);
- ARMword immediate = BIT (22);
- ARMword add_to_base = BIT (23);
- ARMword pre_indexed = BIT (24);
- ARMword offset;
- ARMword addr;
- ARMword sum;
- ARMword base;
-
- BUSUSEDINCPCS;
-
- /* If the writeback bit is set, the pre-index bit must be clear. */
- if (write_back && ! pre_indexed)
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- /* Extract the base address register. */
- addr_reg = LHSReg;
-
- /* Base register cannot be PC. */
- if (addr_reg == 15)
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- /* Extract the source register. */
- src_reg = DESTReg;
-
- /* Source register must be even. */
- if (src_reg & 1)
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- /* Compute the base address. */
- base = state->Reg[addr_reg];
-
- /* Compute the offset. */
- offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state->Reg[RHSReg];
-
- /* Compute the sum of the two. */
- if (add_to_base)
- sum = base + offset;
- else
- sum = base - offset;
-
- /* If this is a pre-indexed mode use the sum. */
- if (pre_indexed)
- addr = sum;
- else
- addr = base;
-
- /* The address must be aligned on a 8 byte boundary. */
- if (addr & 0x7)
- {
-#ifdef ABORTS
- ARMul_DATAABORT (addr);
-#else
- ARMul_UndefInstr (state, instr);
-#endif
- return;
- }
-
- /* For pre indexed or post indexed addressing modes,
- check that the destination registers do not overlap
- the address registers. */
- if ((! pre_indexed || write_back)
- && ( addr_reg == src_reg
- || addr_reg == src_reg + 1))
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- /* Load the words. */
- ARMul_StoreWordN (state, addr, state->Reg[src_reg]);
- ARMul_StoreWordN (state, addr + 4, state->Reg[src_reg + 1]);
-
- if (state->Aborted)
- {
- TAKEABORT;
- return;
- }
-
- /* Do the post addressing and writeback. */
- if (! pre_indexed)
- addr = sum;
-
- if (! pre_indexed || write_back)
- state->Reg[addr_reg] = addr;
-}
-
-/* This function does the work of storing a word from a STR instruction. */
-
-static unsigned
-StoreWord (ARMul_State * state, ARMword instr, ARMword address)
-{
- BUSUSEDINCPCN;
-#ifndef MODE32
- if (DESTReg == 15)
- state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
-#endif
-#ifdef MODE32
- ARMul_StoreWordN (state, address, DEST);
-#else
- if (VECTORACCESS (address) || ADDREXCEPT (address))
- {
- INTERNALABORT (address);
- (void) ARMul_LoadWordN (state, address);
- }
- else
- ARMul_StoreWordN (state, address, DEST);
-#endif
- if (state->Aborted)
- {
- TAKEABORT;
- return state->lateabtSig;
- }
- return TRUE;
-}
-
-#ifdef MODET
-/* This function does the work of storing a byte for a STRH instruction. */
-
-static unsigned
-StoreHalfWord (ARMul_State * state, ARMword instr, ARMword address)
-{
- BUSUSEDINCPCN;
-
-#ifndef MODE32
- if (DESTReg == 15)
- state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
-#endif
-
-#ifdef MODE32
- ARMul_StoreHalfWord (state, address, DEST);
-#else
- if (VECTORACCESS (address) || ADDREXCEPT (address))
- {
- INTERNALABORT (address);
- (void) ARMul_LoadHalfWord (state, address);
- }
- else
- ARMul_StoreHalfWord (state, address, DEST);
-#endif
-
- if (state->Aborted)
- {
- TAKEABORT;
- return state->lateabtSig;
- }
-
- return TRUE;
-}
-
-#endif /* MODET */
-
-/* This function does the work of storing a byte for a STRB instruction. */
-
-static unsigned
-StoreByte (ARMul_State * state, ARMword instr, ARMword address)
-{
- BUSUSEDINCPCN;
-#ifndef MODE32
- if (DESTReg == 15)
- state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
-#endif
-#ifdef MODE32
- ARMul_StoreByte (state, address, DEST);
-#else
- if (VECTORACCESS (address) || ADDREXCEPT (address))
- {
- INTERNALABORT (address);
- (void) ARMul_LoadByte (state, address);
- }
- else
- ARMul_StoreByte (state, address, DEST);
-#endif
- if (state->Aborted)
- {
- TAKEABORT;
- return (state->lateabtSig);
- }
- UNDEF_LSRBPC;
- return TRUE;
-}
-
-/* This function does the work of loading the registers listed in an LDM
- instruction, when the S bit is clear. The code here is always increment
- after, it's up to the caller to get the input address correct and to
- handle base register modification.a */
-
-static void
-LoadMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase)
-{
- ARMword dest, temp;
-
- UNDEF_LSMNoRegs;
- UNDEF_LSMPCBase;
- UNDEF_LSMBaseInListWb;
- BUSUSEDINCPCS;
-#ifndef MODE32
- if (ADDREXCEPT (address))
- INTERNALABORT (address);
-#endif
- if (BIT (21) && LHSReg != 15)
- LSBase = WBBase;
-
- for (temp = 0; !BIT (temp); temp++)
- ; /* N cycle first */
-
- dest = ARMul_LoadWordN (state, address);
-
- if (!state->abortSig && !state->Aborted)
- state->Reg[temp++] = dest;
- else if (!state->Aborted)
- {
- XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
- state->Aborted = ARMul_DataAbortV;
- }
-
- for (; temp < 16; temp++) /* S cycles from here on */
- if (BIT (temp))
- { /* load this register */
- address += 4;
- dest = ARMul_LoadWordS (state, address);
-
- if (!state->abortSig && !state->Aborted)
- state->Reg[temp] = dest;
- else if (!state->Aborted)
- {
- XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
- state->Aborted = ARMul_DataAbortV;
- }
- }
-
- if (BIT (15) && !state->Aborted)
- /* PC is in the reg list. */
- WriteR15Branch (state, PC);
-
- /* To write back the final register. */
- ARMul_Icycles (state, 1, 0L);
-
- if (state->Aborted)
- {
- if (BIT (21) && LHSReg != 15)
- LSBase = WBBase;
- TAKEABORT;
- }
-}
-
-/* This function does the work of loading the registers listed in an LDM
- instruction, when the S bit is set. The code here is always increment
- after, it's up to the caller to get the input address correct and to
- handle base register modification. */
-
-static void
-LoadSMult (ARMul_State * state,
- ARMword instr,
- ARMword address,
- ARMword WBBase)
-{
- ARMword dest, temp;
-
- UNDEF_LSMNoRegs;
- UNDEF_LSMPCBase;
- UNDEF_LSMBaseInListWb;
-
- BUSUSEDINCPCS;
-
-#ifndef MODE32
- if (ADDREXCEPT (address))
- INTERNALABORT (address);
-#endif
-
- if (BIT (21) && LHSReg != 15)
- LSBase = WBBase;
-
- if (!BIT (15) && state->Bank != USERBANK)
- {
- /* Temporary reg bank switch. */
- (void) ARMul_SwitchMode (state, state->Mode, USER26MODE);
- UNDEF_LSMUserBankWb;
- }
-
- for (temp = 0; !BIT (temp); temp ++)
- ; /* N cycle first. */
-
- dest = ARMul_LoadWordN (state, address);
-
- if (!state->abortSig)
- state->Reg[temp++] = dest;
- else if (!state->Aborted)
- {
- XScale_set_fsr_far(state, ARMul_CP15_R5_ST_ALIGN, address);
- state->Aborted = ARMul_DataAbortV;
- }
-
- for (; temp < 16; temp++)
- /* S cycles from here on. */
- if (BIT (temp))
- {
- /* Load this register. */
- address += 4;
- dest = ARMul_LoadWordS (state, address);
-
- if (!state->abortSig && !state->Aborted)
- state->Reg[temp] = dest;
- else if (!state->Aborted)
- {
- XScale_set_fsr_far(state, ARMul_CP15_R5_ST_ALIGN, address);
- state->Aborted = ARMul_DataAbortV;
- }
- }
-
- if (BIT (15) && !state->Aborted)
- {
- /* PC is in the reg list. */
-#ifdef MODE32
- if (state->Mode != USER26MODE && state->Mode != USER32MODE)
- {
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
- }
-
- WriteR15 (state, PC);
-#else
- if (state->Mode == USER26MODE || state->Mode == USER32MODE)
- {
- /* Protect bits in user mode. */
- ASSIGNN ((state->Reg[15] & NBIT) != 0);
- ASSIGNZ ((state->Reg[15] & ZBIT) != 0);
- ASSIGNC ((state->Reg[15] & CBIT) != 0);
- ASSIGNV ((state->Reg[15] & VBIT) != 0);
- }
- else
- ARMul_R15Altered (state);
-
- FLUSHPIPE;
-#endif
- }
-
- if (!BIT (15) && state->Mode != USER26MODE && state->Mode != USER32MODE)
- /* Restore the correct bank. */
- (void) ARMul_SwitchMode (state, USER26MODE, state->Mode);
-
- /* To write back the final register. */
- ARMul_Icycles (state, 1, 0L);
-
- if (state->Aborted)
- {
- if (BIT (21) && LHSReg != 15)
- LSBase = WBBase;
-
- TAKEABORT;
- }
-}
-
-/* This function does the work of storing the registers listed in an STM
- instruction, when the S bit is clear. The code here is always increment
- after, it's up to the caller to get the input address correct and to
- handle base register modification. */
-
-static void
-StoreMult (ARMul_State * state, ARMword instr,
- ARMword address, ARMword WBBase)
-{
- ARMword temp;
-
- UNDEF_LSMNoRegs;
- UNDEF_LSMPCBase;
- UNDEF_LSMBaseInListWb;
-
- if (!TFLAG)
- /* N-cycle, increment the PC and update the NextInstr state. */
- BUSUSEDINCPCN;
-
-#ifndef MODE32
- if (VECTORACCESS (address) || ADDREXCEPT (address))
- INTERNALABORT (address);
-
- if (BIT (15))
- PATCHR15;
-#endif
-
- for (temp = 0; !BIT (temp); temp++)
- ; /* N cycle first. */
-
-#ifdef MODE32
- ARMul_StoreWordN (state, address, state->Reg[temp++]);
-#else
- if (state->Aborted)
- {
- (void) ARMul_LoadWordN (state, address);
-
- /* Fake the Stores as Loads. */
- for (; temp < 16; temp++)
- if (BIT (temp))
- {
- /* Save this register. */
- address += 4;
- (void) ARMul_LoadWordS (state, address);
- }
- if (BIT (21) && LHSReg != 15)
- LSBase = WBBase;
- TAKEABORT;
- return;
- }
- else
- ARMul_StoreWordN (state, address, state->Reg[temp++]);
-#endif
-
- if (state->abortSig && !state->Aborted)
- {
- XScale_set_fsr_far(state, ARMul_CP15_R5_ST_ALIGN, address);
- state->Aborted = ARMul_DataAbortV;
- }
-
- if (BIT (21) && LHSReg != 15)
- LSBase = WBBase;
-
- for (; temp < 16; temp++) /* S cycles from here on */
- if (BIT (temp))
- {
- /* Save this register. */
- address += 4;
-
- ARMul_StoreWordS (state, address, state->Reg[temp]);
-
- if (state->abortSig && !state->Aborted)
- {
- XScale_set_fsr_far(state, ARMul_CP15_R5_ST_ALIGN, address);
- state->Aborted = ARMul_DataAbortV;
- }
- }
-
- if (state->Aborted)
- TAKEABORT;
-}
-
-/* This function does the work of storing the registers listed in an STM
- instruction when the S bit is set. The code here is always increment
- after, it's up to the caller to get the input address correct and to
- handle base register modification. */
-
-static void
-StoreSMult (ARMul_State * state,
- ARMword instr,
- ARMword address,
- ARMword WBBase)
-{
- ARMword temp;
-
- UNDEF_LSMNoRegs;
- UNDEF_LSMPCBase;
- UNDEF_LSMBaseInListWb;
-
- BUSUSEDINCPCN;
-
-#ifndef MODE32
- if (VECTORACCESS (address) || ADDREXCEPT (address))
- INTERNALABORT (address);
-
- if (BIT (15))
- PATCHR15;
-#endif
-
- if (state->Bank != USERBANK)
- {
- /* Force User Bank. */
- (void) ARMul_SwitchMode (state, state->Mode, USER26MODE);
- UNDEF_LSMUserBankWb;
- }
-
- for (temp = 0; !BIT (temp); temp++)
- ; /* N cycle first. */
-
-#ifdef MODE32
- ARMul_StoreWordN (state, address, state->Reg[temp++]);
-#else
- if (state->Aborted)
- {
- (void) ARMul_LoadWordN (state, address);
-
- for (; temp < 16; temp++)
- /* Fake the Stores as Loads. */
- if (BIT (temp))
- {
- /* Save this register. */
- address += 4;
-
- (void) ARMul_LoadWordS (state, address);
- }
-
- if (BIT (21) && LHSReg != 15)
- LSBase = WBBase;
-
- TAKEABORT;
-
- return;
- }
- else
- ARMul_StoreWordN (state, address, state->Reg[temp++]);
-#endif
-
- if (state->abortSig && !state->Aborted)
- {
- XScale_set_fsr_far(state, ARMul_CP15_R5_ST_ALIGN, address);
- state->Aborted = ARMul_DataAbortV;
- }
-
- for (; temp < 16; temp++)
- /* S cycles from here on. */
- if (BIT (temp))
- {
- /* Save this register. */
- address += 4;
-
- ARMul_StoreWordS (state, address, state->Reg[temp]);
-
- if (state->abortSig && !state->Aborted)
- {
- XScale_set_fsr_far(state, ARMul_CP15_R5_ST_ALIGN, address);
- state->Aborted = ARMul_DataAbortV;
- }
- }
-
- if (state->Mode != USER26MODE && state->Mode != USER32MODE)
- /* Restore the correct bank. */
- (void) ARMul_SwitchMode (state, USER26MODE, state->Mode);
-
- if (BIT (21) && LHSReg != 15)
- LSBase = WBBase;
-
- if (state->Aborted)
- TAKEABORT;
-}
-
-/* This function does the work of adding two 32bit values
- together, and calculating if a carry has occurred. */
-
-static ARMword
-Add32 (ARMword a1, ARMword a2, int *carry)
-{
- ARMword result = (a1 + a2);
- unsigned int uresult = (unsigned int) result;
- unsigned int ua1 = (unsigned int) a1;
-
- /* If (result == RdLo) and (state->Reg[nRdLo] == 0),
- or (result > RdLo) then we have no carry: */
- if ((uresult == ua1) ? (a2 != 0) : (uresult < ua1))
- *carry = 1;
- else
- *carry = 0;
-
- return (result);
-}
-
-/* This function does the work of multiplying
- two 32bit values to give a 64bit result. */
-
-static unsigned
-Multiply64 (ARMul_State * state, ARMword instr, int msigned, int scc)
-{
- /* Operand register numbers. */
- int nRdHi, nRdLo, nRs, nRm;
- ARMword RdHi = 0, RdLo = 0, Rm;
- /* Cycle count. */
- int scount;
-
- nRdHi = BITS (16, 19);
- nRdLo = BITS (12, 15);
- nRs = BITS (8, 11);
- nRm = BITS (0, 3);
-
- /* Needed to calculate the cycle count. */
- Rm = state->Reg[nRm];
-
- /* Check for illegal operand combinations first. */
- if ( nRdHi != 15
- && nRdLo != 15
- && nRs != 15
- && nRm != 15
- && nRdHi != nRdLo
- && nRdHi != nRm
- && nRdLo != nRm)
- {
- /* Intermediate results. */
- ARMword lo, mid1, mid2, hi;
- int carry;
- ARMword Rs = state->Reg[nRs];
- int sign = 0;
-
- if (msigned)
- {
- /* Compute sign of result and adjust operands if necessary. */
-
- sign = (Rm ^ Rs) & 0x80000000;
-
- if (((signed long) Rm) < 0)
- Rm = -Rm;
-
- if (((signed long) Rs) < 0)
- Rs = -Rs;
- }
-
- /* We can split the 32x32 into four 16x16 operations. This
- ensures that we do not lose precision on 32bit only hosts. */
- lo = ((Rs & 0xFFFF) * (Rm & 0xFFFF));
- mid1 = ((Rs & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
- mid2 = (((Rs >> 16) & 0xFFFF) * (Rm & 0xFFFF));
- hi = (((Rs >> 16) & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
-
- /* We now need to add all of these results together, taking
- care to propogate the carries from the additions. */
- RdLo = Add32 (lo, (mid1 << 16), &carry);
- RdHi = carry;
- RdLo = Add32 (RdLo, (mid2 << 16), &carry);
- RdHi +=
- (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
-
- if (sign)
- {
- /* Negate result if necessary. */
-
- RdLo = ~RdLo;
- RdHi = ~RdHi;
- if (RdLo == 0xFFFFFFFF)
- {
- RdLo = 0;
- RdHi += 1;
- }
- else
- RdLo += 1;
- }
- /* Else undefined result. */
-
- state->Reg[nRdLo] = RdLo;
- state->Reg[nRdHi] = RdHi;
- }
- else
- fprintf (stderr, "sim: MULTIPLY64 - INVALID ARGUMENTS\n");
-
- if (scc)
- {
- /* Ensure that both RdHi and RdLo are used to compute Z,
- but don't let RdLo's sign bit make it to N. */
- ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF));
- }
-
- /* The cycle count depends on whether the instruction is a signed or
- unsigned multiply, and what bits are clear in the multiplier. */
- if (msigned && (Rm & ((unsigned) 1 << 31)))
- /* Invert the bits to make the check against zero. */
- Rm = ~Rm;
-
- if ((Rm & 0xFFFFFF00) == 0)
- scount = 1;
- else if ((Rm & 0xFFFF0000) == 0)
- scount = 2;
- else if ((Rm & 0xFF000000) == 0)
- scount = 3;
- else
- scount = 4;
-
- return 2 + scount;
-}
-
-/* This function does the work of multiplying two 32bit
- values and adding a 64bit value to give a 64bit result. */
-
-static unsigned
-MultiplyAdd64 (ARMul_State * state, ARMword instr, int msigned, int scc)
-{
- unsigned scount;
- ARMword RdLo, RdHi;
- int nRdHi, nRdLo;
- int carry = 0;
-
- nRdHi = BITS (16, 19);
- nRdLo = BITS (12, 15);
-
- RdHi = state->Reg[nRdHi];
- RdLo = state->Reg[nRdLo];
-
- scount = Multiply64 (state, instr, msigned, LDEFAULT);
-
- RdLo = Add32 (RdLo, state->Reg[nRdLo], &carry);
- RdHi = (RdHi + state->Reg[nRdHi]) + carry;
-
- state->Reg[nRdLo] = RdLo;
- state->Reg[nRdHi] = RdHi;
-
- if (scc)
- /* Ensure that both RdHi and RdLo are used to compute Z,
- but don't let RdLo's sign bit make it to N. */
- ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF));
-
- /* Extra cycle for addition. */
- return scount + 1;
-}
generated by cgit v1.1 at 2024-08-24 21:14:27 +0000