More AArch64 simulator improvements.

	* cpustate.c (aarch64_get_FP_half): New function.  Read a vector
	register as a half precision floating point number.
	(aarch64_set_FP_half): New function.  Similar, but for setting
	a half precision register.
	(aarch64_get_thread_id): New function.  Returns the value of the
	CPU's TPIDR register.
	(aarch64_get_FPCR): New function.  Returns the value of the CPU's
	floating point control register.
	(aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
	register.
	* cpustate.h: Add prototypes for new functions.
	* sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
	* memory.c: Use unaligned core access functions for all memory
	reads and writes.
	* simulator.c (HALT_NYI): Generate an error message if tracing
	will not tell the user why the simulator is halting.
	(HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
	(INSTR): New time-saver macro.
	(fldrb_abs): New function.  Loads an 8-bit value using a scaled
	offset.
	(fldrh_abs): New function.  Likewise for 16-bit values.
	(do_vec_SSHL): Allow for negative shift values.
	(do_vec_USHL): Likewise.
	(do_vec_SHL): Correct computation of shift amount.
	(do_vec_SSHR_USHR): Correct decision of signed vs unsigned
	shifts and computation of shift value.
	(clz): New function.  Counts leading zero bits.
	(do_vec_CLZ): New function.  Implements CLZ (vector).
	(do_vec_MOV_element): Call do_vec_CLZ.
	(dexSimpleFPCondCompare): Implement.
	(do_FCVT_half_to_single): New function.  Implements one of the
	FCVT operations.
	(do_FCVT_half_to_double): New function.  Likewise.
	(do_FCVT_single_to_half): New function.  Likewise.
	(do_FCVT_double_to_half): New function.  Likewise.
	(dexSimpleFPDataProc1Source): Call new FCVT functions.
	(do_scalar_SHL): Handle negative shifts.
	(do_scalar_shift): Handle SSHR.
	(do_scalar_USHL): New function.
	(do_double_add): Simplify to just performing a double precision
	add operation.  Move remaining code into...
	(do_scalar_vec): ... New function.
	(dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
	functions.
	(system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
	registers.
	(system_set): New function.
	(do_MSR_immediate): New function.  Stub for now.
	(do_MSR_reg): New function.  Likewise. Partially implements MSR
	instruction.
	(do_SYS): New function.  Stub for now,
	(dexSystem): Call new functions.

1 files changed, 17 insertions, 9 deletions

diff --git a/sim/aarch64/cpustate.h b/sim/aarch64/cpustate.h
index 931e193..49379d6 100644
--- a/sim/aarch64/cpustate.h
+++ b/sim/aarch64/cpustate.h
@@ -168,10 +168,10 @@ typedef union FRegisterValue
   float        s;
   double       d;
 
-  uint64_t    v[2];
-  uint32_t    w[4];
-  uint16_t    h[8];
-  uint8_t     b[16];
+  uint64_t     v[2];
+  uint32_t     w[4];
+  uint16_t     h[8];
+  uint8_t      b[16];
 
   int64_t      V[2];
   int32_t      W[4];
@@ -194,10 +194,10 @@ typedef union FRegisterValue
 
 typedef enum FlagIdx
 {
-  V_IDX,
-  C_IDX,
-  Z_IDX,
-  N_IDX
+  V_IDX = 0,
+  C_IDX = 1,
+  Z_IDX = 2,
+  N_IDX = 3
 } FlagIdx;
 
 typedef enum FlagMask
@@ -216,7 +216,7 @@ typedef uint32_t FlagsRegister;
 
    This register includes IDC, IXC, UFC, OFC, DZC, IOC and QC bits,
    and the floating point N, Z, C, V bits but the latter are unused in
-   aarch64 mode. the sim ignores QC for now.
+   aarch64 mode.  The sim ignores QC for now.
 
    Bit positions are as per the ARMv7 FPSCR register
 
@@ -272,9 +272,12 @@ extern void        aarch64_set_reg_u64 (sim_cpu *, GReg, int, uint64_t);
 extern void        aarch64_set_reg_s64 (sim_cpu *, GReg, int, int64_t);
 
 /* FP Register access functions.  */
+extern float       aarch64_get_FP_half   (sim_cpu *, VReg);
 extern float       aarch64_get_FP_float  (sim_cpu *, VReg);
 extern double      aarch64_get_FP_double (sim_cpu *, VReg);
 extern void        aarch64_get_FP_long_double (sim_cpu *, VReg, FRegister *);
+
+extern void        aarch64_set_FP_half   (sim_cpu *, VReg, float);
 extern void        aarch64_set_FP_float  (sim_cpu *, VReg, float);
 extern void        aarch64_set_FP_double (sim_cpu *, VReg, double);
 extern void        aarch64_set_FP_long_double (sim_cpu *, VReg, FRegister);
@@ -330,4 +333,9 @@ extern double      aarch64_get_vec_double (sim_cpu *, VReg, unsigned);
 extern void        aarch64_set_vec_float  (sim_cpu *, VReg, unsigned, float);
 extern void        aarch64_set_vec_double (sim_cpu *, VReg, unsigned, double);
 
+/* System register accessors.  */
+extern uint64_t	   aarch64_get_thread_id (sim_cpu *);
+extern uint32_t	   aarch64_get_FPCR (sim_cpu *);
+extern void	   aarch64_set_FPCR (sim_cpu *, uint32_t);
+
 #endif /* _CPU_STATE_H  */