Refactoring/cleanup of nios2 opcodes and assembler code.

2014-10-23  Sandra Loosemore  <sandra@codesourcery.com>

	include/opcode/
	* nios2.h (enum iw_format_type): New.
	(struct nios2_opcode): Update comments.  Add size and format fields.
	(NIOS2_INSN_OPTARG): New.
	(REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
	(struct nios2_reg): Add regtype field.
	(GET_INSN_FIELD, SET_INSN_FIELD): Delete.
	(IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
	(IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
	(IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
	(IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
	(IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
	(IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
	(IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
	(IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
	(IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
	(IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
	(IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
	(OP_MASK_OP, OP_SH_OP): Delete.
	(OP_MASK_IOP, OP_SH_IOP): Delete.
	(OP_MASK_IRD, OP_SH_IRD): Delete.
	(OP_MASK_IRT, OP_SH_IRT): Delete.
	(OP_MASK_IRS, OP_SH_IRS): Delete.
	(OP_MASK_ROP, OP_SH_ROP): Delete.
	(OP_MASK_RRD, OP_SH_RRD): Delete.
	(OP_MASK_RRT, OP_SH_RRT): Delete.
	(OP_MASK_RRS, OP_SH_RRS): Delete.
	(OP_MASK_JOP, OP_SH_JOP): Delete.
	(OP_MASK_IMM26, OP_SH_IMM26): Delete.
	(OP_MASK_RCTL, OP_SH_RCTL): Delete.
	(OP_MASK_IMM5, OP_SH_IMM5): Delete.
	(OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
	(OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
	(OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
	(OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
	(OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
	(OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
	(OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
	(OP_MASK_<insn>, OP_MASK): Delete.
	(GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
	(GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
	Include nios2r1.h to define new instruction opcode constants
	and accessors.
	(nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
	(bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
	(bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
	(NUMOPCODES, NUMREGISTERS): Delete.
	* nios2r1.h: New file.

	opcodes/
	* nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
	(nios2_builtin_opcodes): Rename to nios2_r1_opcodes.  Use new
	MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers.  Add
	size and format initializers.  Merge 'b' arguments into 'j'.
	(NIOS2_NUM_OPCODES): Adjust definition.
	(bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
	(nios2_opcodes): Adjust.
	(bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
	* nios2-dis.c (INSNLEN): Update comment.
	(nios2_hash_init, nios2_hash): Delete.
	(OPCODE_HASH_SIZE): New.
	(nios2_r1_extract_opcode): New.
	(nios2_disassembler_state): New.
	(nios2_r1_disassembler_state): New.
	(nios2_init_opcode_hash): Add state parameter.  Adjust to use it.
	(nios2_find_opcode_hash): Use state object.
	(bad_opcode): New.
	(nios2_print_insn_arg): Add op parameter.  Use it to access
	format.  Remove 'b' case.
	(nios2_disassemble): Remove special case for nop.  Remove
	hard-coded instruction size.

	gas/
	* config/tc-nios2.c (nios2_insn_infoS): Add constant_bits field.
	(nios2_arg_infoS, nios2_arg_hash, nios2_arg_lookup): Delete.
	(nios2_control_register_arg_p): Delete.
	(nios2_coproc_reg): Delete.
	(nios2_relax_frag): Remove hard-coded instruction size.
	(md_convert_frag): Use new insn accessor macros.
	(nios2_diagnose_overflow): Remove hard-coded instruction size.
	(md_apply_fix): Likewise.
	(bad_opcode): New.
	(nios2_parse_reg): New.
	(nios2_assemble_expression): Remove prev_reloc parameter.  Adjust
	uses and callers.
	(nios2_assemble_arg_c): New.
	(nios2_assemble_arg_d): New.
	(nios2_assemble_arg_s): New.
	(nios2_assemble_arg_t): New.
	(nios2_assemble_arg_i): New.
	(nios2_assemble_arg_u): New.
	(nios2_assemble_arg_o): New.
	(nios2_assemble_arg_j): New.
	(nios2_assemble_arg_l): New.
	(nios2_assemble_arg_m): New.
	(nios2_assemble_args): New.
	(nios2_assemble_args_dst): Delete.
	(nios2_assemble_args_tsi): Delete.
	(nios2_assemble_args_tsu): Delete.
	(nios2_assemble_args_sto): Delete.
	(nios2_assemble_args_o): Delete.
	(nios2_assemble_args_is): Delete.
	(nios2_assemble_args_m): Delete.
	(nios2_assemble_args_s): Delete.
	(nios2_assemble_args_tis): Delete.
	(nios2_assemble_args_dc): Delete.
	(nios2_assemble_args_cs): Delete.
	(nios2_assemble_args_ds): Delete.
	(nios2_assemble_args_ldst): Delete.
	(nios2_assemble_args_none): Delete.
	(nios2_assemble_args_dsj): Delete.
	(nios2_assemble_args_d): Delete.
	(nios2_assemble_args_b): Delete.
	(nios2_arg_info_structs): Delete.
	(NIOS2_NUM_ARGS): Delete.
	(nios2_consume_arg): Remove insn parameter.  Use new macros.
	Don't check register arguments here.  Remove 'b' case.
	(nios2_consume_separator): Move check for missing separators to...
	(nios2_parse_args): ...here.  Remove special case for optional
	arguments.
	(output_insn): Avoid using hard-coded insn size.
	(output_ubranch): Likewise.
	(output_cbranch): Likewise.
	(output_call): Use new macros.
	(output_addi): Likewise.
	(output_ori): Likewise.
	(output_xori): Likewise.
	(output_movia): Likewise.
	(md_begin): Remove nios2_arg_info_structs initialization.
	(md_assemble): Initialize constant_bits field.  Use
	nios2_parse_args instead of looking up parse function in hash table.

	gdb/
	* nios2-tdep.c (nios2_analyze_prologue): Use new instruction field
	accessors and constants from nios2 opcodes update.
	(nios2_get_next_pc): Likewise.

3 files changed, 580 insertions, 451 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 49fc81d..1841df4 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,27 @@
+2014-10-23  Sandra Loosemore  <sandra@codesourcery.com>
+
+	* nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
+	(nios2_builtin_opcodes): Rename to nios2_r1_opcodes.  Use new
+	MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers.  Add
+	size and format initializers.  Merge 'b' arguments into 'j'.
+	(NIOS2_NUM_OPCODES): Adjust definition.
+	(bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
+	(nios2_opcodes): Adjust.
+	(bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
+	* nios2-dis.c (INSNLEN): Update comment.
+	(nios2_hash_init, nios2_hash): Delete.
+	(OPCODE_HASH_SIZE): New.
+	(nios2_r1_extract_opcode): New.
+	(nios2_disassembler_state): New.
+	(nios2_r1_disassembler_state): New.
+	(nios2_init_opcode_hash): Add state parameter.  Adjust to use it.
+	(nios2_find_opcode_hash): Use state object.
+	(bad_opcode): New.
+	(nios2_print_insn_arg): Add op parameter.  Use it to access
+	format.  Remove 'b' case.
+	(nios2_disassemble): Remove special case for nop.  Remove
+	hard-coded instruction size.
+
 2014-10-21  Jan Beulich  <jbeulich@suse.com>
 
 	* ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
diff --git a/opcodes/nios2-dis.c b/opcodes/nios2-dis.c
index b5c680f..00ee342 100644
--- a/opcodes/nios2-dis.c
+++ b/opcodes/nios2-dis.c
@@ -35,7 +35,7 @@
 #include "elf/nios2.h"
 #endif
 
-/* Length of Nios II instruction in bytes.  */
+/* Default length of Nios II instruction in bytes.  */
 #define INSNLEN 4
 
 /* Data structures used by the opcode hash table.  */
@@ -45,36 +45,66 @@ typedef struct _nios2_opcode_hash
   struct _nios2_opcode_hash *next;
 } nios2_opcode_hash;
 
-static bfd_boolean nios2_hash_init = 0;
-static nios2_opcode_hash *nios2_hash[(OP_MASK_OP) + 1];
+/* Hash table size.  */
+#define OPCODE_HASH_SIZE (IW_R1_OP_UNSHIFTED_MASK + 1)
 
-/* Separate hash table for pseudo-ops.  */
-static nios2_opcode_hash *nios2_ps_hash[(OP_MASK_OP) + 1];
+/* Extract the opcode from an instruction word.  */
+static unsigned int
+nios2_r1_extract_opcode (unsigned int x)
+{
+  return GET_IW_R1_OP (x);
+}
+
+/* Pseudo-ops are stored in a different table than regular instructions.  */
+
+typedef struct _nios2_disassembler_state
+{
+  const struct nios2_opcode *opcodes;
+  const int *num_opcodes;
+  unsigned int (*extract_opcode) (unsigned int);
+  nios2_opcode_hash *hash[OPCODE_HASH_SIZE];
+  nios2_opcode_hash *ps_hash[OPCODE_HASH_SIZE];
+  const struct nios2_opcode *nop;
+  bfd_boolean init;
+} nios2_disassembler_state;
+
+static nios2_disassembler_state
+nios2_r1_disassembler_state = {
+  nios2_r1_opcodes,
+  &nios2_num_r1_opcodes,
+  nios2_r1_extract_opcode,
+  {},
+  {},
+  NULL,
+  0
+};
 
 /* Function to initialize the opcode hash table.  */
 static void
-nios2_init_opcode_hash (void)
+nios2_init_opcode_hash (nios2_disassembler_state *state)
 {
   unsigned int i;
   register const struct nios2_opcode *op;
 
-  for (i = 0; i <= OP_MASK_OP; ++i)
-    nios2_hash[0] = NULL;
-  for (i = 0; i <= OP_MASK_OP; i++)
-    for (op = nios2_opcodes; op < &nios2_opcodes[NUMOPCODES]; op++)
+  for (i = 0; i < OPCODE_HASH_SIZE; i++)
+    for (op = state->opcodes; op < &state->opcodes[*(state->num_opcodes)]; op++)
       {
 	nios2_opcode_hash *new_hash;
 	nios2_opcode_hash **bucket = NULL;
 
 	if ((op->pinfo & NIOS2_INSN_MACRO) == NIOS2_INSN_MACRO)
 	  {
-	    if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)
+	    if (i == state->extract_opcode (op->match)
 		&& (op->pinfo & (NIOS2_INSN_MACRO_MOV | NIOS2_INSN_MACRO_MOVI)
 		    & 0x7fffffff))
-	      bucket = &(nios2_ps_hash[i]);
+	      {
+		bucket = &(state->ps_hash[i]);
+		if (strcmp (op->name, "nop") == 0)
+		  state->nop = op;
+	      }
 	  }
-	else if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
-	  bucket = &(nios2_hash[i]);
+	else if (i == state->extract_opcode (op->match))
+	  bucket = &(state->hash[i]);
 
 	if (bucket)
 	  {
@@ -93,11 +123,12 @@ nios2_init_opcode_hash (void)
 	    *bucket = new_hash;
 	  }
       }
-  nios2_hash_init = 1;
+  state->init = 1;
+
 #ifdef DEBUG_HASHTABLE
-  for (i = 0; i <= OP_MASK_OP; ++i)
+  for (i = 0; i < OPCODE_HASH_SIZE; ++i)
     {
-      nios2_opcode_hash *tmp_hash = nios2_hash[i];
+      nios2_opcode_hash *tmp_hash = state->hash[i];
       printf ("index: 0x%02X	ops: ", i);
       while (tmp_hash != NULL)
 	{
@@ -107,9 +138,9 @@ nios2_init_opcode_hash (void)
       printf ("\n");
     }
 
-  for (i = 0; i <= OP_MASK_OP; ++i)
+  for (i = 0; i < OPCODE_HASH_SIZE; ++i)
     {
-      nios2_opcode_hash *tmp_hash = nios2_ps_hash[i];
+      nios2_opcode_hash *tmp_hash = state->ps_hash[i];
       printf ("index: 0x%02X	ops: ", i);
       while (tmp_hash != NULL)
 	{
@@ -127,19 +158,27 @@ const struct nios2_opcode *
 nios2_find_opcode_hash (unsigned long opcode)
 {
   nios2_opcode_hash *entry;
+  nios2_disassembler_state *state;
+
+  state = &nios2_r1_disassembler_state;
 
   /* Build a hash table to shorten the search time.  */
-  if (!nios2_hash_init)
-    nios2_init_opcode_hash ();
+  if (!state->init)
+    nios2_init_opcode_hash (state);
+
+  /* Check for NOP first.  Both NOP and MOV are macros that expand into
+     an ADD instruction, and we always want to give priority to NOP.  */
+  if (state->nop->match == (opcode & state->nop->mask))
+    return state->nop;
 
   /* First look in the pseudo-op hashtable.  */
-  for (entry = nios2_ps_hash[(opcode >> OP_SH_OP) & OP_MASK_OP];
+  for (entry = state->ps_hash[state->extract_opcode (opcode)];
        entry; entry = entry->next)
     if (entry->opcode->match == (opcode & entry->opcode->mask))
       return entry->opcode;
 
   /* Otherwise look in the main hashtable.  */
-  for (entry = nios2_hash[(opcode >> OP_SH_OP) & OP_MASK_OP];
+  for (entry = state->hash[state->extract_opcode (opcode)];
        entry; entry = entry->next)
     if (entry->opcode->match == (opcode & entry->opcode->mask))
       return entry->opcode;
@@ -191,13 +230,23 @@ nios2_control_regs (void)
   return cached;
 }
 
+/* Helper routine to report internal errors.  */
+static void
+bad_opcode (const struct nios2_opcode *op)
+{
+  fprintf (stderr, "Internal error: broken opcode descriptor for `%s %s'\n",
+	   op->name, op->args);
+  abort ();
+}
+
 /* The function nios2_print_insn_arg uses the character pointed
    to by ARGPTR to determine how it print the next token or separator
    character in the arguments to an instruction.  */
 static int
 nios2_print_insn_arg (const char *argptr,
 		      unsigned long opcode, bfd_vma address,
-		      disassemble_info *info)
+		      disassemble_info *info,
+		      const struct nios2_opcode *op)
 {
   unsigned long i = 0;
   struct nios2_reg *reg_base;
@@ -209,98 +258,180 @@ nios2_print_insn_arg (const char *argptr,
     case ')':
       (*info->fprintf_func) (info->stream, "%c", *argptr);
       break;
-    case 'd':
-      i = GET_INSN_FIELD (RRD, opcode);
-
-      if (GET_INSN_FIELD (OP, opcode) == OP_MATCH_CUSTOM
-	  && GET_INSN_FIELD (CUSTOM_C, opcode) == 0)
-	reg_base = nios2_coprocessor_regs ();
-      else
-	reg_base = nios2_regs;
 
+    case 'd':
+      switch (op->format)
+	{
+	case iw_r_type:
+	  i = GET_IW_R_C (opcode);
+	  reg_base = nios2_regs;
+	  break;
+	case iw_custom_type:
+	  i = GET_IW_CUSTOM_C (opcode);
+	  if (GET_IW_CUSTOM_READC (opcode) == 0)
+	    reg_base = nios2_coprocessor_regs ();
+	  else
+	    reg_base = nios2_regs;
+	  break;
+	default:
+	  bad_opcode (op);
+	}
       if (i < NUMREGNAMES)
 	(*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
       else
 	(*info->fprintf_func) (info->stream, "unknown");
       break;
-    case 's':
-      i = GET_INSN_FIELD (RRS, opcode);
-
-      if (GET_INSN_FIELD (OP, opcode) == OP_MATCH_CUSTOM
-	  && GET_INSN_FIELD (CUSTOM_A, opcode) == 0)
-	reg_base = nios2_coprocessor_regs ();
-      else
-	reg_base = nios2_regs;
 
+    case 's':
+      switch (op->format)
+	{
+	case iw_r_type:
+	  i = GET_IW_R_A (opcode);
+	  reg_base = nios2_regs;
+	  break;
+	case iw_i_type:
+	  i = GET_IW_I_A (opcode);
+	  reg_base = nios2_regs;
+	  break;
+	case iw_custom_type:
+	  i = GET_IW_CUSTOM_A (opcode);
+	  if (GET_IW_CUSTOM_READA (opcode) == 0)
+	    reg_base = nios2_coprocessor_regs ();
+	  else
+	    reg_base = nios2_regs;
+	  break;
+	default:
+	  bad_opcode (op);
+	}
       if (i < NUMREGNAMES)
 	(*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
       else
 	(*info->fprintf_func) (info->stream, "unknown");
       break;
-    case 't':
-      i = GET_INSN_FIELD (RRT, opcode);
-
-      if (GET_INSN_FIELD (OP, opcode) == OP_MATCH_CUSTOM
-	  && GET_INSN_FIELD (CUSTOM_B, opcode) == 0)
-	reg_base = nios2_coprocessor_regs ();
-      else
-	reg_base = nios2_regs;
 
+    case 't':
+      switch (op->format)
+	{
+	case iw_r_type:
+	  i = GET_IW_R_B (opcode);
+	  reg_base = nios2_regs;
+	  break;
+	case iw_i_type:
+	  i = GET_IW_I_B (opcode);
+	  reg_base = nios2_regs;
+	  break;
+	case iw_custom_type:
+	  i = GET_IW_CUSTOM_B (opcode);
+	  if (GET_IW_CUSTOM_READB (opcode) == 0)
+	    reg_base = nios2_coprocessor_regs ();
+	  else
+	    reg_base = nios2_regs;
+	  break;
+	default:
+	  bad_opcode (op);
+	}
       if (i < NUMREGNAMES)
 	(*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
       else
 	(*info->fprintf_func) (info->stream, "unknown");
       break;
+
     case 'i':
       /* 16-bit signed immediate.  */
-      i = (signed) (GET_INSN_FIELD (IMM16, opcode) << 16) >> 16;
+      switch (op->format)
+	{
+	case iw_i_type:
+	  i = (signed) (GET_IW_I_IMM16 (opcode) << 16) >> 16;
+	  break;
+	default:
+	  bad_opcode (op);
+	}
       (*info->fprintf_func) (info->stream, "%ld", i);
       break;
+
     case 'u':
       /* 16-bit unsigned immediate.  */
-      i = GET_INSN_FIELD (IMM16, opcode);
+      switch (op->format)
+	{
+	case iw_i_type:
+	  i = GET_IW_I_IMM16 (opcode);
+	  break;
+	default:
+	  bad_opcode (op);
+	}
       (*info->fprintf_func) (info->stream, "%ld", i);
       break;
+
     case 'o':
       /* 16-bit signed immediate address offset.  */
-      i = (signed) (GET_INSN_FIELD (IMM16, opcode) << 16) >> 16;
+      switch (op->format)
+	{
+	case iw_i_type:
+	  i = (signed) (GET_IW_I_IMM16 (opcode) << 16) >> 16;
+	  break;
+	default:
+	  bad_opcode (op);
+	}
       address = address + 4 + i;
       (*info->print_address_func) (address, info);
       break;
-    case 'p':
-      /* 5-bit unsigned immediate.  */
-      i = GET_INSN_FIELD (CACHE_OPX, opcode);
-      (*info->fprintf_func) (info->stream, "%ld", i);
-      break;
+
     case 'j':
       /* 5-bit unsigned immediate.  */
-      i = GET_INSN_FIELD (IMM5, opcode);
+      switch (op->format)
+	{
+	case iw_r_type:
+	  i = GET_IW_R_IMM5 (opcode);
+	  break;
+	default:
+	  bad_opcode (op);
+	}
       (*info->fprintf_func) (info->stream, "%ld", i);
       break;
+
     case 'l':
       /* 8-bit unsigned immediate.  */
-      /* FIXME - not yet implemented */
-      i = GET_INSN_FIELD (CUSTOM_N, opcode);
+      switch (op->format)
+	{
+	case iw_custom_type:
+	  i = GET_IW_CUSTOM_N (opcode);
+	  break;
+	default:
+	  bad_opcode (op);
+	}
       (*info->fprintf_func) (info->stream, "%lu", i);
       break;
+
     case 'm':
       /* 26-bit unsigned immediate.  */
-      i = GET_INSN_FIELD (IMM26, opcode);
+      switch (op->format)
+	{
+	case iw_j_type:
+	  i = GET_IW_J_IMM26 (opcode);
+	  break;
+	default:
+	  bad_opcode (op);
+	}
       /* This translates to an address because it's only used in call
 	 instructions.  */
       address = (address & 0xf0000000) | (i << 2);
       (*info->print_address_func) (address, info);
       break;
+
     case 'c':
       /* Control register index.  */
-      i = GET_INSN_FIELD (IMM5, opcode);
+      switch (op->format)
+	{
+	case iw_r_type:
+	  i = GET_IW_R_IMM5 (opcode);
+	  break;
+	default:
+	  bad_opcode (op);
+	}
       reg_base = nios2_control_regs ();
       (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
       break;
-    case 'b':
-      i = GET_INSN_FIELD (IMM5, opcode);
-      (*info->fprintf_func) (info->stream, "%ld", i);
-      break;
+
     default:
       (*info->fprintf_func) (info->stream, "unknown");
       break;
@@ -332,46 +463,28 @@ nios2_disassemble (bfd_vma address, unsigned long opcode,
 
   if (op != NULL)
     {
-      bfd_boolean is_nop = FALSE;
-      if (op->pinfo == NIOS2_INSN_MACRO_MOV)
-	{
-	  /* Check for mov r0, r0 and change to nop.  */
-	  int dst, src;
-	  dst = GET_INSN_FIELD (RRD, opcode);
-	  src = GET_INSN_FIELD (RRS, opcode);
-	  if (dst == 0 && src == 0)
-	    {
-	      (*info->fprintf_func) (info->stream, "nop");
-	      is_nop = TRUE;
-	    }
-	  else
-	    (*info->fprintf_func) (info->stream, "%s", op->name);
-	}
-      else
-	(*info->fprintf_func) (info->stream, "%s", op->name);
-
-      if (!is_nop)
+      const char *argstr = op->args;
+      (*info->fprintf_func) (info->stream, "%s", op->name);
+      if (argstr != NULL && *argstr != '\0')
 	{
-	  const char *argstr = op->args;
-	  if (argstr != NULL && *argstr != '\0')
+	  (*info->fprintf_func) (info->stream, "\t");
+	  while (*argstr != '\0')
 	    {
-	      (*info->fprintf_func) (info->stream, "\t");
-	      while (*argstr != '\0')
-		{
-		  nios2_print_insn_arg (argstr, opcode, address, info);
-		  ++argstr;
-		}
+	      nios2_print_insn_arg (argstr, opcode, address, info, op);
+	      ++argstr;
 	    }
 	}
+      /* Tell the caller how far to advance the program counter.  */
+      info->bytes_per_chunk = op->size;
+      return op->size;
     }
   else
     {
       /* Handle undefined instructions.  */
       info->insn_type = dis_noninsn;
       (*info->fprintf_func) (info->stream, "0x%lx", opcode);
+      return INSNLEN;
     }
-  /* Tell the caller how far to advance the program counter.  */
-  return INSNLEN;
 }
 
 
diff --git a/opcodes/nios2-opc.c b/opcodes/nios2-opc.c
index 47a7ee4..a12a2f8 100644
--- a/opcodes/nios2-opc.c
+++ b/opcodes/nios2-opc.c
@@ -28,136 +28,136 @@
 
 const struct nios2_reg nios2_builtin_regs[] = {
   /* Standard register names.  */
-  {"zero", 0},
-  {"at", 1},			/* assembler temporary */
-  {"r2", 2},
-  {"r3", 3},
-  {"r4", 4},
-  {"r5", 5},
-  {"r6", 6},
-  {"r7", 7},
-  {"r8", 8},
-  {"r9", 9},
-  {"r10", 10},
-  {"r11", 11},
-  {"r12", 12},
-  {"r13", 13},
-  {"r14", 14},
-  {"r15", 15},
-  {"r16", 16},
-  {"r17", 17},
-  {"r18", 18},
-  {"r19", 19},
-  {"r20", 20},
-  {"r21", 21},
-  {"r22", 22},
-  {"r23", 23},
-  {"et", 24},
-  {"bt", 25},
-  {"gp", 26},			/* global pointer */
-  {"sp", 27},			/* stack pointer */
-  {"fp", 28},			/* frame pointer */
-  {"ea", 29},			/* exception return address */
-  {"sstatus", 30},		/* saved processor status */
-  {"ra", 31},			/* return address */
+  {"zero", 0, REG_NORMAL},
+  {"at", 1, REG_NORMAL},			/* assembler temporary */
+  {"r2", 2, REG_NORMAL},
+  {"r3", 3, REG_NORMAL},
+  {"r4", 4, REG_NORMAL},
+  {"r5", 5, REG_NORMAL},
+  {"r6", 6, REG_NORMAL},
+  {"r7", 7, REG_NORMAL},
+  {"r8", 8, REG_NORMAL},
+  {"r9", 9, REG_NORMAL},
+  {"r10", 10, REG_NORMAL},
+  {"r11", 11, REG_NORMAL},
+  {"r12", 12, REG_NORMAL},
+  {"r13", 13, REG_NORMAL},
+  {"r14", 14, REG_NORMAL},
+  {"r15", 15, REG_NORMAL},
+  {"r16", 16, REG_NORMAL},
+  {"r17", 17, REG_NORMAL},
+  {"r18", 18, REG_NORMAL},
+  {"r19", 19, REG_NORMAL},
+  {"r20", 20, REG_NORMAL},
+  {"r21", 21, REG_NORMAL},
+  {"r22", 22, REG_NORMAL},
+  {"r23", 23, REG_NORMAL},
+  {"et", 24, REG_NORMAL},
+  {"bt", 25, REG_NORMAL},
+  {"gp", 26, REG_NORMAL},			/* global pointer */
+  {"sp", 27, REG_NORMAL},			/* stack pointer */
+  {"fp", 28, REG_NORMAL},			/* frame pointer */
+  {"ea", 29, REG_NORMAL},			/* exception return address */
+  {"sstatus", 30, REG_NORMAL},			/* saved processor status */
+  {"ra", 31, REG_NORMAL},			/* return address */
 
   /* Alternative names for special registers.  */
-  {"r0", 0},
-  {"r1", 1},
-  {"r24", 24},
-  {"r25", 25},
-  {"r26", 26},
-  {"r27", 27},
-  {"r28", 28},
-  {"r29", 29},
-  {"r30", 30},
-  {"ba", 30},			/* breakpoint return address */
-  {"r31", 31},
+  {"r0", 0, REG_NORMAL},
+  {"r1", 1, REG_NORMAL},
+  {"r24", 24, REG_NORMAL},
+  {"r25", 25, REG_NORMAL},
+  {"r26", 26, REG_NORMAL},
+  {"r27", 27, REG_NORMAL},
+  {"r28", 28, REG_NORMAL},
+  {"r29", 29, REG_NORMAL},
+  {"r30", 30, REG_NORMAL},
+  {"ba", 30, REG_NORMAL},			/* breakpoint return address */
+  {"r31", 31, REG_NORMAL},
 
   /* Control register names.  */
-  {"status", 0},
-  {"estatus", 1},
-  {"bstatus", 2},
-  {"ienable", 3},
-  {"ipending", 4},
-  {"cpuid", 5},
-  {"ctl6", 6},
-  {"exception", 7},
-  {"pteaddr", 8},
-  {"tlbacc", 9},
-  {"tlbmisc", 10},
-  {"eccinj", 11},
-  {"badaddr", 12},
-  {"config", 13},
-  {"mpubase", 14},
-  {"mpuacc", 15},
-  {"ctl16", 16},
-  {"ctl17", 17},
-  {"ctl18", 18},
-  {"ctl19", 19},
-  {"ctl20", 20},
-  {"ctl21", 21},
-  {"ctl22", 22},
-  {"ctl23", 23},
-  {"ctl24", 24},
-  {"ctl25", 25},
-  {"ctl26", 26},
-  {"ctl27", 27},
-  {"ctl28", 28},
-  {"ctl29", 29},
-  {"ctl30", 30},
-  {"ctl31", 31},
+  {"status", 0, REG_CONTROL},
+  {"estatus", 1, REG_CONTROL},
+  {"bstatus", 2, REG_CONTROL},
+  {"ienable", 3, REG_CONTROL},
+  {"ipending", 4, REG_CONTROL},
+  {"cpuid", 5, REG_CONTROL},
+  {"ctl6", 6, REG_CONTROL},
+  {"exception", 7, REG_CONTROL},
+  {"pteaddr", 8, REG_CONTROL},
+  {"tlbacc", 9, REG_CONTROL},
+  {"tlbmisc", 10, REG_CONTROL},
+  {"eccinj", 11, REG_CONTROL},
+  {"badaddr", 12, REG_CONTROL},
+  {"config", 13, REG_CONTROL},
+  {"mpubase", 14, REG_CONTROL},
+  {"mpuacc", 15, REG_CONTROL},
+  {"ctl16", 16, REG_CONTROL},
+  {"ctl17", 17, REG_CONTROL},
+  {"ctl18", 18, REG_CONTROL},
+  {"ctl19", 19, REG_CONTROL},
+  {"ctl20", 20, REG_CONTROL},
+  {"ctl21", 21, REG_CONTROL},
+  {"ctl22", 22, REG_CONTROL},
+  {"ctl23", 23, REG_CONTROL},
+  {"ctl24", 24, REG_CONTROL},
+  {"ctl25", 25, REG_CONTROL},
+  {"ctl26", 26, REG_CONTROL},
+  {"ctl27", 27, REG_CONTROL},
+  {"ctl28", 28, REG_CONTROL},
+  {"ctl29", 29, REG_CONTROL},
+  {"ctl30", 30, REG_CONTROL},
+  {"ctl31", 31, REG_CONTROL},
 
   /* Alternative names for special control registers.  */
-  {"ctl0", 0},
-  {"ctl1", 1},
-  {"ctl2", 2},
-  {"ctl3", 3},
-  {"ctl4", 4},
-  {"ctl5", 5},
-  {"ctl7", 7},
-  {"ctl8", 8},
-  {"ctl9", 9},
-  {"ctl10", 10},
-  {"ctl11", 11},
-  {"ctl12", 12},
-  {"ctl13", 13},
-  {"ctl14", 14},
-  {"ctl15", 15},
+  {"ctl0", 0, REG_CONTROL},
+  {"ctl1", 1, REG_CONTROL},
+  {"ctl2", 2, REG_CONTROL},
+  {"ctl3", 3, REG_CONTROL},
+  {"ctl4", 4, REG_CONTROL},
+  {"ctl5", 5, REG_CONTROL},
+  {"ctl7", 7, REG_CONTROL},
+  {"ctl8", 8, REG_CONTROL},
+  {"ctl9", 9, REG_CONTROL},
+  {"ctl10", 10, REG_CONTROL},
+  {"ctl11", 11, REG_CONTROL},
+  {"ctl12", 12, REG_CONTROL},
+  {"ctl13", 13, REG_CONTROL},
+  {"ctl14", 14, REG_CONTROL},
+  {"ctl15", 15, REG_CONTROL},
 
   /* Coprocessor register names.  */
-  {"c0", 0},
-  {"c1", 1},
-  {"c2", 2},
-  {"c3", 3},
-  {"c4", 4},
-  {"c5", 5},
-  {"c6", 6},
-  {"c7", 7},
-  {"c8", 8},
-  {"c9", 9},
-  {"c10", 10},
-  {"c11", 11},
-  {"c12", 12},
-  {"c13", 13},
-  {"c14", 14},
-  {"c15", 15},
-  {"c16", 16},
-  {"c17", 17},
-  {"c18", 18},
-  {"c19", 19},
-  {"c20", 20},
-  {"c21", 21},
-  {"c22", 22},
-  {"c23", 23},
-  {"c24", 24},
-  {"c25", 25},
-  {"c26", 26},
-  {"c27", 27},
-  {"c28", 28},
-  {"c29", 29},
-  {"c30", 30},
-  {"c31", 31},
+  {"c0", 0, REG_COPROCESSOR},
+  {"c1", 1, REG_COPROCESSOR},
+  {"c2", 2, REG_COPROCESSOR},
+  {"c3", 3, REG_COPROCESSOR},
+  {"c4", 4, REG_COPROCESSOR},
+  {"c5", 5, REG_COPROCESSOR},
+  {"c6", 6, REG_COPROCESSOR},
+  {"c7", 7, REG_COPROCESSOR},
+  {"c8", 8, REG_COPROCESSOR},
+  {"c9", 9, REG_COPROCESSOR},
+  {"c10", 10, REG_COPROCESSOR},
+  {"c11", 11, REG_COPROCESSOR},
+  {"c12", 12, REG_COPROCESSOR},
+  {"c13", 13, REG_COPROCESSOR},
+  {"c14", 14, REG_COPROCESSOR},
+  {"c15", 15, REG_COPROCESSOR},
+  {"c16", 16, REG_COPROCESSOR},
+  {"c17", 17, REG_COPROCESSOR},
+  {"c18", 18, REG_COPROCESSOR},
+  {"c19", 19, REG_COPROCESSOR},
+  {"c20", 20, REG_COPROCESSOR},
+  {"c21", 21, REG_COPROCESSOR},
+  {"c22", 22, REG_COPROCESSOR},
+  {"c23", 23, REG_COPROCESSOR},
+  {"c24", 24, REG_COPROCESSOR},
+  {"c25", 25, REG_COPROCESSOR},
+  {"c26", 26, REG_COPROCESSOR},
+  {"c27", 27, REG_COPROCESSOR},
+  {"c28", 28, REG_COPROCESSOR},
+  {"c29", 29, REG_COPROCESSOR},
+  {"c30", 30, REG_COPROCESSOR},
+  {"c31", 31, REG_COPROCESSOR},
 };
 
 #define NIOS2_NUM_REGS \
@@ -172,244 +172,236 @@ int nios2_num_regs = NIOS2_NUM_REGS;
 
 /* This is the opcode table used by the Nios II GNU as, disassembler
    and GDB.  */
-const struct nios2_opcode nios2_builtin_opcodes[] =
+const struct nios2_opcode nios2_r1_opcodes[] =
 {
-  /* { name, args, args_test, num_args,
-       match, mask, pinfo, overflow_msg } */
-  {"add", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_ADD, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"addi", "t,s,i", "t,s,i,E", 3,
-   OP_MATCH_ADDI, OP_MASK_IOP, NIOS2_INSN_ADDI, signed_immed16_overflow},
-  {"subi", "t,s,i", "t,s,i,E", 3,
-   OP_MATCH_ADDI, OP_MASK_IOP, NIOS2_INSN_MACRO, signed_immed16_overflow},
-  {"and", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_AND, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"andhi", "t,s,u", "t,s,u,E", 3,
-   OP_MATCH_ANDHI, OP_MASK_IOP, 0, unsigned_immed16_overflow},
-  {"andi", "t,s,u", "t,s,u,E", 3,
-   OP_MATCH_ANDI, OP_MASK_IOP, NIOS2_INSN_ANDI, unsigned_immed16_overflow},
-  {"beq", "s,t,o", "s,t,o,E", 3,
-   OP_MATCH_BEQ, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow},
-  {"bge", "s,t,o", "s,t,o,E", 3,
-   OP_MATCH_BGE, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow},
-  {"bgeu", "s,t,o", "s,t,o,E", 3,
-   OP_MATCH_BGEU, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow},
-  {"bgt", "s,t,o", "s,t,o,E", 3,
-   OP_MATCH_BLT, OP_MASK_IOP, NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH,
-   branch_target_overflow},
-  {"bgtu", "s,t,o", "s,t,o,E", 3,
-   OP_MATCH_BLTU, OP_MASK_IOP, NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH,
-   branch_target_overflow},
-  {"ble", "s,t,o", "s,t,o,E", 3,
-   OP_MATCH_BGE, OP_MASK_IOP, NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH,
-   branch_target_overflow},
-  {"bleu", "s,t,o", "s,t,o,E", 3,
-   OP_MATCH_BGEU, OP_MASK_IOP, NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH,
-   branch_target_overflow},
-  {"blt", "s,t,o", "s,t,o,E", 3,
-   OP_MATCH_BLT, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow},
-  {"bltu", "s,t,o", "s,t,o,E", 3,
-   OP_MATCH_BLTU, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow},
-  {"bne", "s,t,o", "s,t,o,E", 3,
-   OP_MATCH_BNE, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow},
-  {"br", "o", "o,E", 1,
-   OP_MATCH_BR, OP_MASK_IOP, NIOS2_INSN_UBRANCH, branch_target_overflow},
-  {"break", "b", "b,E", 1,
-   OP_MATCH_BREAK, OP_MASK_BREAK, 0, no_overflow},
-  {"bret", "", "E", 0,
-   OP_MATCH_BRET, OP_MASK, 0, no_overflow},
-  {"flushd", "i(s)", "i(s)E", 2,
-   OP_MATCH_FLUSHD, OP_MASK_IOP, 0, signed_immed16_overflow},
-  {"flushda", "i(s)", "i(s)E", 2,
-   OP_MATCH_FLUSHDA, OP_MASK_IOP, 0, signed_immed16_overflow},
-  {"flushi", "s", "s,E", 1,
-   OP_MATCH_FLUSHI, OP_MASK_FLUSHI, 0, no_overflow},
-  {"flushp", "", "E", 0,
-   OP_MATCH_FLUSHP, OP_MASK, 0, no_overflow},
-  {"initd", "i(s)", "i(s)E", 2,
-   OP_MATCH_INITD, OP_MASK_IOP, 0, signed_immed16_overflow},
-  {"initda", "i(s)", "i(s)E", 2,
-   OP_MATCH_INITDA, OP_MASK_IOP, 0, signed_immed16_overflow},
-  {"initi", "s", "s,E", 1,
-   OP_MATCH_INITI, OP_MASK_INITI, 0, no_overflow},
-  {"call", "m", "m,E", 1,
-   OP_MATCH_CALL, OP_MASK_IOP, NIOS2_INSN_CALL, call_target_overflow},
-  {"callr", "s", "s,E", 1,
-   OP_MATCH_CALLR, OP_MASK_CALLR, 0, no_overflow},
-  {"cmpeq", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_CMPEQ, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"cmpeqi", "t,s,i", "t,s,i,E", 3,
-   OP_MATCH_CMPEQI, OP_MASK_IOP, 0, signed_immed16_overflow},
-  {"cmpge", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_CMPGE, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"cmpgei", "t,s,i", "t,s,i,E", 3,
-   OP_MATCH_CMPGEI, OP_MASK_IOP, 0, signed_immed16_overflow},
-  {"cmpgeu", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_CMPGEU, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"cmpgeui", "t,s,u", "t,s,u,E", 3,
-   OP_MATCH_CMPGEUI, OP_MASK_IOP, 0, unsigned_immed16_overflow},
-  {"cmpgt", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_CMPLT, OP_MASK_ROPX | OP_MASK_ROP, NIOS2_INSN_MACRO, no_overflow},
-  {"cmpgti", "t,s,i", "t,s,i,E", 3,
-   OP_MATCH_CMPGEI, OP_MASK_IOP, NIOS2_INSN_MACRO, signed_immed16_overflow},
-  {"cmpgtu", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_CMPLTU, OP_MASK_ROPX | OP_MASK_ROP, NIOS2_INSN_MACRO, no_overflow},
-  {"cmpgtui", "t,s,u", "t,s,u,E", 3,
-   OP_MATCH_CMPGEUI, OP_MASK_IOP, NIOS2_INSN_MACRO, unsigned_immed16_overflow},
-  {"cmple", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_CMPGE, OP_MASK_ROPX | OP_MASK_ROP, NIOS2_INSN_MACRO, no_overflow},
-  {"cmplei", "t,s,i", "t,s,i,E", 3,
-   OP_MATCH_CMPLTI, OP_MASK_IOP, NIOS2_INSN_MACRO, signed_immed16_overflow},
-  {"cmpleu", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_CMPGEU, OP_MASK_ROPX | OP_MASK_ROP, NIOS2_INSN_MACRO, no_overflow},
-  {"cmpleui", "t,s,u", "t,s,u,E", 3,
-   OP_MATCH_CMPLTUI, OP_MASK_IOP, NIOS2_INSN_MACRO, unsigned_immed16_overflow},
-  {"cmplt", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_CMPLT, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"cmplti", "t,s,i", "t,s,i,E", 3,
-   OP_MATCH_CMPLTI, OP_MASK_IOP, 0, signed_immed16_overflow},
-  {"cmpltu", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_CMPLTU, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"cmpltui", "t,s,u", "t,s,u,E", 3,
-   OP_MATCH_CMPLTUI, OP_MASK_IOP, 0, unsigned_immed16_overflow},
-  {"cmpne", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_CMPNE, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"cmpnei", "t,s,i", "t,s,i,E", 3,
-   OP_MATCH_CMPNEI, OP_MASK_IOP, 0, signed_immed16_overflow},
-  {"div", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_DIV, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"divu", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_DIVU, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"jmp", "s", "s,E", 1,
-   OP_MATCH_JMP, OP_MASK_JMP, 0, no_overflow},
-  {"jmpi", "m", "m,E", 1,
-   OP_MATCH_JMPI, OP_MASK_IOP, 0, no_overflow},
-  {"ldb", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_LDB, OP_MASK_IOP, 0, address_offset_overflow},
-  {"ldbio", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_LDBIO, OP_MASK_IOP, 0, address_offset_overflow},
-  {"ldbu", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_LDBU, OP_MASK_IOP, 0, address_offset_overflow},
-  {"ldbuio", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_LDBUIO, OP_MASK_IOP, 0, address_offset_overflow},
-  {"ldh", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_LDH, OP_MASK_IOP, 0, address_offset_overflow},
-  {"ldhio", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_LDHIO, OP_MASK_IOP, 0, address_offset_overflow},
-  {"ldhu", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_LDHU, OP_MASK_IOP, 0, address_offset_overflow},
-  {"ldhuio", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_LDHUIO, OP_MASK_IOP, 0, address_offset_overflow},
-  {"ldl", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_LDL, OP_MASK_IOP, 0, address_offset_overflow},
-  {"ldw", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_LDW, OP_MASK_IOP, 0, address_offset_overflow},
-  {"ldwio", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_LDWIO, OP_MASK_IOP, 0, address_offset_overflow},
-  {"mov", "d,s", "d,s,E", 2,
-   OP_MATCH_ADD, OP_MASK_RRT|OP_MASK_ROPX|OP_MASK_ROP, NIOS2_INSN_MACRO_MOV,
-   no_overflow},
-  {"movhi", "t,u", "t,u,E", 2,
-   OP_MATCH_ORHI, OP_MASK_IRS|OP_MASK_IOP, NIOS2_INSN_MACRO_MOVI,
-   unsigned_immed16_overflow},
-  {"movui", "t,u", "t,u,E", 2,
-   OP_MATCH_ORI, OP_MASK_IRS|OP_MASK_IOP, NIOS2_INSN_MACRO_MOVI,
-   unsigned_immed16_overflow},
-  {"movi", "t,i", "t,i,E", 2,
-   OP_MATCH_ADDI, OP_MASK_IRS|OP_MASK_IOP, NIOS2_INSN_MACRO_MOVI,
-   signed_immed16_overflow},
-  /* movia expands to two instructions so there is no mask or match */
-  {"movia", "t,o", "t,o,E", 2,
-   OP_MATCH_ORHI, OP_MASK_IOP, NIOS2_INSN_MACRO_MOVIA, no_overflow},
-  {"mul", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_MUL, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"muli", "t,s,i", "t,s,i,E", 3,
-   OP_MATCH_MULI, OP_MASK_IOP, 0, signed_immed16_overflow},
-  {"mulxss", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_MULXSS, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"mulxsu", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_MULXSU, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"mulxuu", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_MULXUU, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"nextpc", "d", "d,E", 1,
-   OP_MATCH_NEXTPC, OP_MASK_NEXTPC, 0, no_overflow},
-  {"nop", "", "E", 0,
-   OP_MATCH_ADD, OP_MASK, NIOS2_INSN_MACRO_MOV, no_overflow},
-  {"nor", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_NOR, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"or", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_OR, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"orhi", "t,s,u", "t,s,u,E", 3,
-   OP_MATCH_ORHI, OP_MASK_IOP, 0, unsigned_immed16_overflow},
-  {"ori", "t,s,u", "t,s,u,E", 3,
-   OP_MATCH_ORI, OP_MASK_IOP, NIOS2_INSN_ORI, unsigned_immed16_overflow},
-  {"rdctl", "d,c", "d,c,E", 2,
-   OP_MATCH_RDCTL, OP_MASK_RDCTL, 0, no_overflow},
-  {"rdprs", "t,s,i", "t,s,i,E", 3,
-   OP_MATCH_RDPRS, OP_MASK_IOP, 0, unsigned_immed16_overflow},
-  {"ret", "", "E", 0,
-   OP_MATCH_RET, OP_MASK, 0, no_overflow},
-  {"rol", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_ROL, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"roli", "d,s,j", "d,s,j,E", 3,
-   OP_MATCH_ROLI, OP_MASK_ROLI, 0, unsigned_immed5_overflow},
-  {"ror", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_ROR, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"sll", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_SLL, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"slli", "d,s,j", "d,s,j,E", 3,
-   OP_MATCH_SLLI, OP_MASK_SLLI, 0, unsigned_immed5_overflow},
-  {"sra", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_SRA, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"srai", "d,s,j", "d,s,j,E", 3,
-   OP_MATCH_SRAI, OP_MASK_SRAI, 0, unsigned_immed5_overflow},
-  {"srl", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_SRL, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"srli", "d,s,j", "d,s,j,E", 3,
-   OP_MATCH_SRLI, OP_MASK_SRLI, 0, unsigned_immed5_overflow},
-  {"stb", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_STB, OP_MASK_IOP, 0, address_offset_overflow},
-  {"stbio", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_STBIO, OP_MASK_IOP, 0, address_offset_overflow},
-  {"stc", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_STC, OP_MASK_IOP, 0, address_offset_overflow},
-  {"sth", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_STH, OP_MASK_IOP, 0, address_offset_overflow},
-  {"sthio", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_STHIO, OP_MASK_IOP, 0, address_offset_overflow},
-  {"stw", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_STW, OP_MASK_IOP, 0, address_offset_overflow},
-  {"stwio", "t,i(s)", "t,i(s)E", 3,
-   OP_MATCH_STWIO, OP_MASK_IOP, 0, address_offset_overflow},
-  {"sub", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_SUB, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"sync", "", "E", 0,
-   OP_MATCH_SYNC, OP_MASK_SYNC, 0, no_overflow},
-  {"trap", "b", "b,E", 1,
-   OP_MATCH_TRAP, OP_MASK_TRAP, 0, no_overflow},
-  {"eret", "", "E", 0,
-   OP_MATCH_ERET, OP_MASK, 0, no_overflow},
-  {"custom", "l,d,s,t", "l,d,s,t,E", 4,
-   OP_MATCH_CUSTOM, OP_MASK_ROP, 0, custom_opcode_overflow},
-  {"wrctl", "c,s", "c,s,E", 2,
-   OP_MATCH_WRCTL, OP_MASK_WRCTL, 0, no_overflow},
-  {"wrprs", "d,s", "d,s,E", 2,
-   OP_MATCH_WRPRS, OP_MASK_RRT|OP_MASK_ROPX|OP_MASK_ROP, 0, no_overflow},
-  {"xor", "d,s,t", "d,s,t,E", 3,
-   OP_MATCH_XOR, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
-  {"xorhi", "t,s,u", "t,s,u,E", 3,
-   OP_MATCH_XORHI, OP_MASK_IOP, 0, unsigned_immed16_overflow},
-  {"xori", "t,s,u", "t,s,u,E", 3,
-   OP_MATCH_XORI, OP_MASK_IOP, NIOS2_INSN_XORI, unsigned_immed16_overflow}
+  /* { name, args, args_test, num_args, size, format,
+       match, mask, pinfo, overflow } */
+  {"add", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_ADD, MASK_R1_ADD, 0, no_overflow},
+  {"addi", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
+   MATCH_R1_ADDI, MASK_R1_ADDI, NIOS2_INSN_ADDI, signed_immed16_overflow},
+  {"and", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_AND, MASK_R1_AND, 0, no_overflow},
+  {"andhi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
+   MATCH_R1_ANDHI, MASK_R1_ANDHI, 0, unsigned_immed16_overflow},
+  {"andi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
+   MATCH_R1_ANDI, MASK_R1_ANDI, NIOS2_INSN_ANDI, unsigned_immed16_overflow},
+  {"beq", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
+   MATCH_R1_BEQ, MASK_R1_BEQ, NIOS2_INSN_CBRANCH, branch_target_overflow},
+  {"bge", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
+   MATCH_R1_BGE, MASK_R1_BGE, NIOS2_INSN_CBRANCH, branch_target_overflow},
+  {"bgeu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
+   MATCH_R1_BGEU, MASK_R1_BGEU, NIOS2_INSN_CBRANCH, branch_target_overflow},
+  {"bgt", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
+   MATCH_R1_BGT, MASK_R1_BGT,
+   NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
+  {"bgtu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
+   MATCH_R1_BGTU, MASK_R1_BGTU,
+   NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
+  {"ble", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
+   MATCH_R1_BLE, MASK_R1_BLE,
+   NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
+  {"bleu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
+   MATCH_R1_BLEU, MASK_R1_BLEU,
+   NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
+  {"blt", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
+   MATCH_R1_BLT, MASK_R1_BLT, NIOS2_INSN_CBRANCH, branch_target_overflow},
+  {"bltu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
+   MATCH_R1_BLTU, MASK_R1_BLTU, NIOS2_INSN_CBRANCH, branch_target_overflow},
+  {"bne", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
+   MATCH_R1_BNE, MASK_R1_BNE, NIOS2_INSN_CBRANCH, branch_target_overflow},
+  {"br", "o", "o,E", 1, 4, iw_i_type,
+   MATCH_R1_BR, MASK_R1_BR, NIOS2_INSN_UBRANCH, branch_target_overflow},
+  {"break", "j", "j,E", 1, 4, iw_r_type,
+   MATCH_R1_BREAK, MASK_R1_BREAK, NIOS2_INSN_OPTARG, no_overflow},
+  {"bret", "", "E", 0, 4, iw_r_type,
+   MATCH_R1_BRET, MASK_R1_BRET, 0, no_overflow},
+  {"call", "m", "m,E", 1, 4, iw_j_type,
+   MATCH_R1_CALL, MASK_R1_CALL, NIOS2_INSN_CALL, call_target_overflow},
+  {"callr", "s", "s,E", 1, 4, iw_r_type,
+   MATCH_R1_CALLR, MASK_R1_CALLR, 0, no_overflow},
+  {"cmpeq", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_CMPEQ, MASK_R1_CMPEQ, 0, no_overflow},
+  {"cmpeqi", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
+   MATCH_R1_CMPEQI, MASK_R1_CMPEQI, 0, signed_immed16_overflow},
+  {"cmpge", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_CMPGE, MASK_R1_CMPGE, 0, no_overflow},
+  {"cmpgei", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
+   MATCH_R1_CMPGEI, MASK_R1_CMPGEI, 0, signed_immed16_overflow},
+  {"cmpgeu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_CMPGEU, MASK_R1_CMPGEU, 0, no_overflow},
+  {"cmpgeui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
+   MATCH_R1_CMPGEUI, MASK_R1_CMPGEUI, 0, unsigned_immed16_overflow},
+  {"cmpgt", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_CMPGT, MASK_R1_CMPGT, NIOS2_INSN_MACRO, no_overflow},
+  {"cmpgti", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
+   MATCH_R1_CMPGTI, MASK_R1_CMPGTI, NIOS2_INSN_MACRO, signed_immed16_overflow},
+  {"cmpgtu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_CMPGTU, MASK_R1_CMPGTU, NIOS2_INSN_MACRO, no_overflow},
+  {"cmpgtui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
+   MATCH_R1_CMPGTUI, MASK_R1_CMPGTUI,
+   NIOS2_INSN_MACRO, unsigned_immed16_overflow},
+  {"cmple", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_CMPLE, MASK_R1_CMPLE, NIOS2_INSN_MACRO, no_overflow},
+  {"cmplei", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
+   MATCH_R1_CMPLEI, MASK_R1_CMPLEI, NIOS2_INSN_MACRO, signed_immed16_overflow},
+  {"cmpleu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_CMPLEU, MASK_R1_CMPLEU, NIOS2_INSN_MACRO, no_overflow},
+  {"cmpleui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
+   MATCH_R1_CMPLEUI, MASK_R1_CMPLEUI,
+   NIOS2_INSN_MACRO, unsigned_immed16_overflow},
+  {"cmplt", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_CMPLT, MASK_R1_CMPLT, 0, no_overflow},
+  {"cmplti", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
+   MATCH_R1_CMPLTI, MASK_R1_CMPLTI, 0, signed_immed16_overflow},
+  {"cmpltu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_CMPLTU, MASK_R1_CMPLTU, 0, no_overflow},
+  {"cmpltui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
+   MATCH_R1_CMPLTUI, MASK_R1_CMPLTUI, 0, unsigned_immed16_overflow},
+  {"cmpne", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_CMPNE, MASK_R1_CMPNE, 0, no_overflow},
+  {"cmpnei", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
+   MATCH_R1_CMPNEI, MASK_R1_CMPNEI, 0, signed_immed16_overflow},
+  {"custom", "l,d,s,t", "l,d,s,t,E", 4, 4, iw_custom_type,
+   MATCH_R1_CUSTOM, MASK_R1_CUSTOM, 0, custom_opcode_overflow},
+  {"div", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_DIV, MASK_R1_DIV, 0, no_overflow},
+  {"divu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_DIVU, MASK_R1_DIVU, 0, no_overflow},
+  {"eret", "", "E", 0, 4, iw_r_type,
+   MATCH_R1_ERET, MASK_R1_ERET, 0, no_overflow},
+  {"flushd", "i(s)", "i(s),E", 2, 4, iw_i_type,
+   MATCH_R1_FLUSHD, MASK_R1_FLUSHD, 0, address_offset_overflow},
+  {"flushda", "i(s)", "i(s),E", 2, 4, iw_i_type,
+   MATCH_R1_FLUSHDA, MASK_R1_FLUSHDA, 0, address_offset_overflow},
+  {"flushi", "s", "s,E", 1, 4, iw_r_type,
+   MATCH_R1_FLUSHI, MASK_R1_FLUSHI, 0, no_overflow},
+  {"flushp", "", "E", 0, 4, iw_r_type,
+   MATCH_R1_FLUSHP, MASK_R1_FLUSHP, 0, no_overflow},
+  {"initd", "i(s)", "i(s),E", 2, 4, iw_i_type,
+   MATCH_R1_INITD, MASK_R1_INITD, 0, address_offset_overflow},
+  {"initda", "i(s)", "i(s),E", 2, 4, iw_i_type,
+   MATCH_R1_INITDA, MASK_R1_INITDA, 0, address_offset_overflow},
+  {"initi", "s", "s,E", 1, 4, iw_r_type,
+   MATCH_R1_INITI, MASK_R1_INITI, 0, no_overflow},
+  {"jmp", "s", "s,E", 1, 4, iw_r_type,
+   MATCH_R1_JMP, MASK_R1_JMP, 0, no_overflow},
+  {"jmpi", "m", "m,E", 1, 4, iw_j_type,
+   MATCH_R1_JMPI, MASK_R1_JMPI, 0, call_target_overflow},
+  {"ldb", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
+   MATCH_R1_LDB, MASK_R1_LDB, 0, address_offset_overflow},
+  {"ldbio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
+   MATCH_R1_LDBIO, MASK_R1_LDBIO, 0, address_offset_overflow},
+  {"ldbu", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
+   MATCH_R1_LDBU, MASK_R1_LDBU, 0, address_offset_overflow},
+  {"ldbuio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
+   MATCH_R1_LDBUIO, MASK_R1_LDBUIO, 0, address_offset_overflow},
+  {"ldh", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
+   MATCH_R1_LDH, MASK_R1_LDH, 0, address_offset_overflow},
+  {"ldhio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
+   MATCH_R1_LDHIO, MASK_R1_LDHIO, 0, address_offset_overflow},
+  {"ldhu", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
+   MATCH_R1_LDHU, MASK_R1_LDHU, 0, address_offset_overflow},
+  {"ldhuio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
+   MATCH_R1_LDHUIO, MASK_R1_LDHUIO, 0, address_offset_overflow},
+  {"ldw", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
+   MATCH_R1_LDW, MASK_R1_LDW, 0, address_offset_overflow},
+  {"ldwio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
+   MATCH_R1_LDWIO, MASK_R1_LDWIO, 0, address_offset_overflow},
+  {"mov", "d,s", "d,s,E", 2, 4, iw_r_type,
+   MATCH_R1_MOV, MASK_R1_MOV, NIOS2_INSN_MACRO_MOV, no_overflow},
+  {"movhi", "t,u", "t,u,E", 2, 4, iw_i_type,
+   MATCH_R1_MOVHI, MASK_R1_MOVHI,
+   NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow},
+  {"movi", "t,i", "t,i,E", 2, 4, iw_i_type,
+   MATCH_R1_MOVI, MASK_R1_MOVI, NIOS2_INSN_MACRO_MOVI, signed_immed16_overflow},
+  {"movia", "t,o", "t,o,E", 2, 4, iw_i_type,
+   MATCH_R1_ORHI, MASK_R1_ORHI, NIOS2_INSN_MACRO_MOVIA, no_overflow},
+  {"movui", "t,u", "t,u,E", 2, 4, iw_i_type,
+   MATCH_R1_MOVUI, MASK_R1_MOVUI,
+   NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow},
+  {"mul", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_MUL, MASK_R1_MUL, 0, no_overflow},
+  {"muli", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
+   MATCH_R1_MULI, MASK_R1_MULI, 0, signed_immed16_overflow},
+  {"mulxss", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_MULXSS, MASK_R1_MULXSS, 0, no_overflow},
+  {"mulxsu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_MULXSU, MASK_R1_MULXSU, 0, no_overflow},
+  {"mulxuu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_MULXUU, MASK_R1_MULXUU, 0, no_overflow},
+  {"nextpc", "d", "d,E", 1, 4, iw_r_type,
+   MATCH_R1_NEXTPC, MASK_R1_NEXTPC, 0, no_overflow},
+  {"nop", "", "E", 0, 4, iw_r_type,
+   MATCH_R1_NOP, MASK_R1_NOP, NIOS2_INSN_MACRO_MOV, no_overflow},
+  {"nor", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_NOR, MASK_R1_NOR, 0, no_overflow},
+  {"or", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_OR, MASK_R1_OR, 0, no_overflow},
+  {"orhi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
+   MATCH_R1_ORHI, MASK_R1_ORHI, 0, unsigned_immed16_overflow},
+  {"ori", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
+   MATCH_R1_ORI, MASK_R1_ORI, NIOS2_INSN_ORI, unsigned_immed16_overflow},
+  {"rdctl", "d,c", "d,c,E", 2, 4, iw_r_type,
+   MATCH_R1_RDCTL, MASK_R1_RDCTL, 0, no_overflow},
+  {"rdprs", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
+   MATCH_R1_RDPRS, MASK_R1_RDPRS, 0, signed_immed16_overflow},
+  {"ret", "", "E", 0, 4, iw_r_type,
+   MATCH_R1_RET, MASK_R1_RET, 0, no_overflow},
+  {"rol", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_ROL, MASK_R1_ROL, 0, no_overflow},
+  {"roli", "d,s,j", "d,s,j,E", 3, 4, iw_r_type,
+   MATCH_R1_ROLI, MASK_R1_ROLI, 0, unsigned_immed5_overflow},
+  {"ror", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_ROR, MASK_R1_ROR, 0, no_overflow},
+  {"sll", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_SLL, MASK_R1_SLL, 0, no_overflow},
+  {"slli", "d,s,j", "d,s,j,E", 3, 4, iw_r_type,
+   MATCH_R1_SLLI, MASK_R1_SLLI, 0, unsigned_immed5_overflow},
+  {"sra", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_SRA, MASK_R1_SRA, 0, no_overflow},
+  {"srai", "d,s,j", "d,s,j,E", 3, 4, iw_r_type,
+   MATCH_R1_SRAI, MASK_R1_SRAI, 0, unsigned_immed5_overflow},
+  {"srl", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_SRL, MASK_R1_SRL, 0, no_overflow},
+  {"srli", "d,s,j", "d,s,j,E", 3, 4, iw_r_type,
+   MATCH_R1_SRLI, MASK_R1_SRLI, 0, unsigned_immed5_overflow},
+  {"stb", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
+   MATCH_R1_STB, MASK_R1_STB, 0, address_offset_overflow},
+  {"stbio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
+   MATCH_R1_STBIO, MASK_R1_STBIO, 0, address_offset_overflow},
+  {"sth", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
+   MATCH_R1_STH, MASK_R1_STH, 0, address_offset_overflow},
+  {"sthio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
+   MATCH_R1_STHIO, MASK_R1_STHIO, 0, address_offset_overflow},
+  {"stw", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
+   MATCH_R1_STW, MASK_R1_STW, 0, address_offset_overflow},
+  {"stwio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
+   MATCH_R1_STWIO, MASK_R1_STWIO, 0, address_offset_overflow},
+  {"sub", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_SUB, MASK_R1_SUB, 0, no_overflow},
+  {"subi", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
+   MATCH_R1_SUBI, MASK_R1_SUBI, NIOS2_INSN_MACRO, signed_immed16_overflow},
+  {"sync", "", "E", 0, 4, iw_r_type,
+   MATCH_R1_SYNC, MASK_R1_SYNC, 0, no_overflow},
+  {"trap", "j", "j,E", 1, 4, iw_r_type,
+   MATCH_R1_TRAP, MASK_R1_TRAP, NIOS2_INSN_OPTARG, no_overflow},
+  {"wrctl", "c,s", "c,s,E", 2, 4, iw_r_type,
+   MATCH_R1_WRCTL, MASK_R1_WRCTL, 0, no_overflow},
+  {"wrprs", "d,s", "d,s,E", 2, 4, iw_r_type,
+   MATCH_R1_WRPRS, MASK_R1_WRPRS, 0, no_overflow},
+  {"xor", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
+   MATCH_R1_XOR, MASK_R1_XOR, 0, no_overflow},
+  {"xorhi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
+   MATCH_R1_XORHI, MASK_R1_XORHI, 0, unsigned_immed16_overflow},
+  {"xori", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
+   MATCH_R1_XORI, MASK_R1_XORI, NIOS2_INSN_XORI, unsigned_immed16_overflow}
 };
 
 #define NIOS2_NUM_OPCODES \
-       ((sizeof nios2_builtin_opcodes) / (sizeof (nios2_builtin_opcodes[0])))
-const int bfd_nios2_num_builtin_opcodes = NIOS2_NUM_OPCODES;
+       ((sizeof nios2_r1_opcodes) / (sizeof (nios2_r1_opcodes[0])))
+const int nios2_num_r1_opcodes = NIOS2_NUM_OPCODES;
 
-/* This is not const to allow for dynamic extensions to the
-   built-in instruction set. */
-struct nios2_opcode *nios2_opcodes =
-  (struct nios2_opcode *) nios2_builtin_opcodes;
-int bfd_nios2_num_opcodes = NIOS2_NUM_OPCODES;
+struct nios2_opcode *nios2_opcodes = (struct nios2_opcode *) nios2_r1_opcodes;
+int nios2_num_opcodes = NIOS2_NUM_OPCODES;
 #undef NIOS2_NUM_OPCODES