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| author | H.J. Lu <hjl.tools@gmail.com> | 2007-09-20 20:13:26 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2007-09-20 20:13:26 +0000 |
| commit | 20afcfb756e30b8fa84544ff141dc14364ffbcc5 (patch) | |
| tree | b3fd46e68e0cc42e52261d076d84fa2d9da3add3 /opcodes | |
| parent | f3b1e08efea8eb836809b4dea4bfe7a0d10ba542 (diff) | |
| download | gdb-20afcfb756e30b8fa84544ff141dc14364ffbcc5.zip gdb-20afcfb756e30b8fa84544ff141dc14364ffbcc5.tar.gz gdb-20afcfb756e30b8fa84544ff141dc14364ffbcc5.tar.bz2 | |
gas/testsuite/
2007-09-20 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/sib.s: Add more eiz tests.
* gas/i386/x86-64-sib.s: Add more riz tests.
* gas/i386/sib-intel.d: Updated.
* gas/i386/sib.d: Likewise.
* gas/i386/x86-64-sib-intel.d: Likewise.
* gas/i386/x86-64-sib.d: Likewise.
opcodes/
2007-09-20 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_extended): Display eiz for [eiz*1 + offset].
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/i386-dis.c | 12 |
2 files changed, 15 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 88be05e..584e24c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,9 @@ 2007-09-20 H.J. Lu <hongjiu.lu@intel.com> + * i386-dis.c (OP_E_extended): Display eiz for [eiz*1 + offset]. + +2007-09-20 H.J. Lu <hongjiu.lu@intel.com> + PR 658 * 386-dis.c (index64): New. (index32): Likewise. diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 9a45e91..ecb428f 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -6314,6 +6314,7 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex) int havesib; int havebase; int haveindex; + int needindex; int base; int index = 0; int scale = 0; @@ -6368,7 +6369,15 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex) break; } - havedisp = havebase || (havesib && (haveindex || scale != 0)); + /* In 32bit mode, we need index register to tell [offset] from + [eiz*1 + offset]. */ + needindex = (havesib + && !havebase + && !haveindex + && address_mode == mode_32bit); + havedisp = (havebase + || needindex + || (havesib && (haveindex || scale != 0))); if (!intel_syntax) if (modrm.mod != 0 || (base & 7) == 5) @@ -6402,6 +6411,7 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex) /* ESP/RSP won't allow index. If base isn't ESP/RSP, print index to tell base + index from base. */ if (scale != 0 + || needindex || haveindex || (havebase && base != ESP_REG_NUM)) { |