diff options
| author | Andrew Waterman <andrew@sifive.com> | 2017-03-13 12:46:33 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2017-03-30 13:00:16 -0700 |
| commit | c6f578b62090bbbf8458aa75fe1638a922e8d338 (patch) | |
| tree | 350c755578e6448f904a4107086be3e817beedaa /opcodes | |
| parent | e02a1075c7f8af60f789d0fcf337aa9d8bca861b (diff) | |
| download | gdb-c6f578b62090bbbf8458aa75fe1638a922e8d338.zip gdb-c6f578b62090bbbf8458aa75fe1638a922e8d338.tar.gz gdb-c6f578b62090bbbf8458aa75fe1638a922e8d338.tar.bz2 | |
RISC-V: Fix [dis]assembly of srai/srli
These were simple copy/paste errors from the compressed left shift
pattern, which can't have a 0-register.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 8 |
2 files changed, 11 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 0d149f1..21ca15a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2017-03-13 Andrew Waterman <andrew@sifive.com> + + * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode. + <srl> Likewise. + <srai> Likewise. + <sra> Likewise. + 2017-03-27 Alan Modra <amodra@gmail.com> PR 21303 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 867a026..da33600 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -210,14 +210,14 @@ const struct riscv_opcode riscv_opcodes[] = {"sll", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS }, {"sll", "I", "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 }, {"sll", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS }, -{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS }, +{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, INSN_ALIAS }, {"srli", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 }, -{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS }, +{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, INSN_ALIAS }, {"srl", "I", "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 }, {"srl", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS }, -{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS }, +{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, INSN_ALIAS }, {"srai", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 }, -{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS }, +{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, INSN_ALIAS }, {"sra", "I", "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 }, {"sra", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS }, {"sub", "C", "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS }, |