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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2016-11-09 15:30:35 +0100 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@synopsys.com> | 2016-11-22 12:34:51 +0100 |
| commit | c4b943d7aed5edbfc31aa1e9dc9e7bcf108d76a0 (patch) | |
| tree | 8d9627c44264a1f14c0649339f9b95797e487e7f /opcodes | |
| parent | 08dc996fedde9143cda25720961684087b133640 (diff) | |
| download | gdb-c4b943d7aed5edbfc31aa1e9dc9e7bcf108d76a0.zip gdb-c4b943d7aed5edbfc31aa1e9dc9e7bcf108d76a0.tar.gz gdb-c4b943d7aed5edbfc31aa1e9dc9e7bcf108d76a0.tar.bz2 | |
[ARC] Fix printing 'b' mnemonics.
gas/
2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/b.d: Update test result.
opcode/
2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
* arc-tbl.h: Reorder conditional flags with delay flags for 'b'
instructions.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/arc-tbl.h | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index b78e70d..9cd641a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2016-11-22 Claudiu Zissulescu <claziss@synopsys.com> + + * arc-tbl.h: Reorder conditional flags with delay flags for 'b' + instructions. + 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define. diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h index 3246d8d..c6e246e 100644 --- a/opcodes/arc-tbl.h +++ b/opcodes/arc-tbl.h @@ -1394,7 +1394,7 @@ { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM25_A16_5 }, { C_D }}, /* b<.d><cc> s21 00000ssssssssss0SSSSSSSSSSNQQQQQ. */ -{ "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A16_5 }, { C_D, C_CC }}, +{ "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A16_5 }, { C_CC, C_D }}, /* bbit0<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01110. */ { "bbit0", 0x0801000E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }}, |