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| author | Andrew Burgess <andrew.burgess@embecosm.com> | 2016-09-27 12:06:01 +0100 |
|---|---|---|
| committer | Andrew Burgess <andrew.burgess@embecosm.com> | 2016-11-04 22:46:51 +0000 |
| commit | b437d035ddf4e4c0c566c577ee059790ed28ad9b (patch) | |
| tree | 54da51c86dd768e89abcbb808a9a9c614fe87a6f /opcodes | |
| parent | 848ac659685fba46ce8816400db705f60c8040f7 (diff) | |
| download | gdb-b437d035ddf4e4c0c566c577ee059790ed28ad9b.zip gdb-b437d035ddf4e4c0c566c577ee059790ed28ad9b.tar.gz gdb-b437d035ddf4e4c0c566c577ee059790ed28ad9b.tar.bz2 | |
arc/nps400: Validate address type operands correctly
When we match against an address type operand within an instruction it
is important that we match exactly the right address type operand early
on, during the opcode selection phase. If we wait until the operand
insertion phase to check that we have the correct address operand, then
it is too late to select an alternative opcode. This becomes important
only when we have multiple opcodes with the same mnemonic, and operand
lists that differ only in the type of the address operands.
This commit fixes this issue, and adds some example instructions that
require this issue to be fixed (the instructions are identical except
for the address type operand).
gas/ChangeLog:
* config/tc-arc.c (find_opcode_match): Use insert function to
validate matching address type operands.
* testsuite/gas/arc/nps400-10.d: New file.
* testsuite/gas/arc/nps400-10.s: New file.
opcodes/ChangeLog:
* arc-opc.c (arc_flag_operands): Add F_DI14.
(arc_flag_classes): Add C_DI14.
* arc-nps400-tbl.h: Add new exc instructions.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/arc-nps400-tbl.h | 14 | ||||
| -rw-r--r-- | opcodes/arc-opc.c | 8 |
3 files changed, 26 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 03b851a..b58ad90 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com> + + * arc-opc.c (arc_flag_operands): Add F_DI14. + (arc_flag_classes): Add C_DI14. + * arc-nps400-tbl.h: Add new exc instructions. + 2016-11-03 Graham Markall <graham.markall@embecosm.com> * arc-dis.c (arc_insn_length): Return length 8 for instructions with diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h index 8585450..bfc2dee 100644 --- a/opcodes/arc-nps400-tbl.h +++ b/opcodes/arc-nps400-tbl.h @@ -713,3 +713,17 @@ XLDST_LIKE("xst", 0xe) /* dcmac a,[cm:A],[cm:b],size */ { "dcmac", 0x500007c023000000, 0xf80007ffffc00000, ARC_OPCODE_ARC700, PROTOCOL_DECODE, NPS400, { NPS_RA_64, BRAKET, NPS_CM, COLON, NPS_UIMM16_0_64, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_RBdouble_64, BRAKETdup, NPS_PROTO_SIZE }, { 0 }}, + +/* Atomic Operations. */ + +/* exc<.di><.f> a,a,[xa:b] */ +{ "exc", 0x48060c21, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XA, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }}, + +/* exc<.di><.f> a,a,[sd:b] */ +{ "exc", 0x48060c61, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_SD, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }}, + +/* exc<.di><.f> a,a,[xd:b] */ +{ "exc", 0x48060c81, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XD, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }}, + +/* exc<.di><.f> a,a,[b] */ +{ "exc", 0x48060c01, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }}, diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c index 58b26ea..0395345 100644 --- a/opcodes/arc-opc.c +++ b/opcodes/arc-opc.c @@ -1249,7 +1249,9 @@ const struct arc_flag_operand arc_flag_operands[] = { "di", 1, 1, 5, 1 }, #define F_DI11 (F_DI5 + 1) { "di", 1, 1, 11, 1 }, -#define F_DI15 (F_DI11 + 1) +#define F_DI14 (F_DI11 + 1) + { "di", 1, 1, 14, 1 }, +#define F_DI15 (F_DI14 + 1) { "di", 1, 1, 15, 1 }, /* ARCv2 specific. */ @@ -1407,7 +1409,9 @@ const struct arc_flag_class arc_flag_classes[] = #define C_DI20 (C_DHARD + 1) { F_CLASS_OPTIONAL, { F_DI11, F_NULL }}, -#define C_DI16 (C_DI20 + 1) +#define C_DI14 (C_DI20 + 1) + { F_CLASS_OPTIONAL, { F_DI14, F_NULL }}, +#define C_DI16 (C_DI14 + 1) { F_CLASS_OPTIONAL, { F_DI15, F_NULL }}, #define C_DI26 (C_DI16 + 1) { F_CLASS_OPTIONAL, { F_DI5, F_NULL }}, |