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authorYoshinori Sato <ysato@users.sourceforge.jp>2015-12-15 09:26:56 +0000
committerNick Clifton <nickc@redhat.com>2015-12-15 09:26:56 +0000
commita117b0a51cd3c768453c244a3754c1b9a77e74fc (patch)
treefd573106470e4c963aa723316530c87ed5ba2a36 /opcodes/rx-decode.opc
parentef603459d553034a3f4daeb9c8c673f5ef3e4ed0 (diff)
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Add support for RX V2 Instruction Set
binutils * readelf.c(get_machine_flags): Add v2 flag. gas * config/rx-defs.h(rx_cpu_type): Add RXV2 type. * config/tc-rx.c(cpu_type_list): New type lookup table. (md_parse_option): Use lookup table for choose cpu. (md_show_usage): Add rxv2 for mcpu option. * doc/c-rx.texi: Likewise. * config/rx-parse.y: Add v2 instructions and ACC register. (rx_check_v2): check v2 type. include/elf * rx.h(E_FLAG_RX_V2): New RXv2 type. include/opcode * rx.h: Add new instructions. opcoes * rx-deocde.opc(rx_decode_opcode): Add new instructions pattern. * rx-dis.c(register_name): Add new register. gas/testsuite * gas/rx/emaca.d: New. * gas/rx/emaca.sm: New. * gas/rx/emsba.d: New. * gas/rx/emsba.sm: New. * gas/rx/emula.d: New. * gas/rx/emula.sm: New. * gas/rx/fadd.d: Add new pattern. * gas/rx/fadd.sm: Add new pattern. * gas/rx/fmul.d: Add new pattern. * gas/rx/fmul.sm: Add new pattern. * gas/rx/fsqrt.d: New. * gas/rx/fsqrt.sm: New. * gas/rx/fsub.d: Add new pattern. * gas/rx/fsub.sm: Add new pattern. * gas/rx/ftou.d: New. * gas/rx/ftou.sm: New. * gas/rx/maclh.d: New. * gas/rx/maclh.sm: New. * gas/rx/maclo.d: Add new pattern. * gas/rx/maclo.sm: Add new pattern. * gas/rx/macros.inc: Add new register. * gas/rx/movco.d: New. * gas/rx/movco.sm: New. * gas/rx/movli.d: New. * gas/rx/movli.sm: New. * gas/rx/msbhi.d: New. * gas/rx/msbhi.sm: New. * gas/rx/msblh.d: New. * gas/rx/msblh.sm: New. * gas/rx/msblo.d: New. * gas/rx/msblo.sm: New. * gas/rx/mullh.d: New. * gas/rx/mullh.sm: New. * gas/rx/mvfacgu.d: New. * gas/rx/mvfacgu.sm: New. * gas/rx/mvfachi.d: Add new pattern. * gas/rx/mvfachi.sm: Add new pattern. * gas/rx/mvfaclo.d: Add new pattern. * gas/rx/mvfaclo.sm: Add new pattern. * gas/rx/mvfacmi.d: Add new pattern. * gas/rx/mvfacmi.sm: Add new pattern. * gas/rx/mvfc.d: Add new pattern. * gas/rx/mvtacgu.d: New. * gas/rx/mvtacgu.sm: New. * gas/rx/mvtc.d: Add new pattern. * gas/rx/popc.d: Add new pattern. * gas/rx/pushc.d: Add new pattern. * gas/rx/racl.d: New. * gas/rx/racl.sm: New. * gas/rx/racw.d: Add new pattern. * gas/rx/racw.sm: Add new pattern. * gas/rx/rdacl.d: New. * gas/rx/rdacl.sm: New. * gas/rx/rdacw.d: New. * gas/rx/rdacw.sm: New. * gas/rx/rx.exp: Add option. * gas/rx/stnz.d: Add new pattern. * gas/rx/stnz.sm: Add new pattern. * gas/rx/stz.d: Add new pattern. * gas/rx/stz.sm: Add new pattern. * gas/rx/utof.d: New. * gas/rx/utof.sm: New.
Diffstat (limited to 'opcodes/rx-decode.opc')
-rw-r--r--opcodes/rx-decode.opc115
1 files changed, 95 insertions, 20 deletions
diff --git a/opcodes/rx-decode.opc b/opcodes/rx-decode.opc
index 12f6893..a3cc751 100644
--- a/opcodes/rx-decode.opc
+++ b/opcodes/rx-decode.opc
@@ -844,35 +844,35 @@ rx_decode_opcode (unsigned long pc AU,
/*----------------------------------------------------------------------*/
/* HI/LO stuff */
-/** 1111 1101 0000 0000 srca srcb mulhi %1, %2 */
- ID(mulhi); SR(srca); S2R(srcb); F_____;
+/** 1111 1101 0000 a000 srca srcb mulhi %1, %2, %0 */
+ ID(mulhi); DR(a+32); SR(srca); S2R(srcb); F_____;
-/** 1111 1101 0000 0001 srca srcb mullo %1, %2 */
- ID(mullo); SR(srca); S2R(srcb); F_____;
+/** 1111 1101 0000 a001 srca srcb mullo %1, %2, %0 */
+ ID(mullo); DR(a+32); SR(srca); S2R(srcb); F_____;
-/** 1111 1101 0000 0100 srca srcb machi %1, %2 */
- ID(machi); SR(srca); S2R(srcb); F_____;
+/** 1111 1101 0000 a100 srca srcb machi %1, %2, %0 */
+ ID(machi); DR(a+32); SR(srca); S2R(srcb); F_____;
-/** 1111 1101 0000 0101 srca srcb maclo %1, %2 */
- ID(maclo); SR(srca); S2R(srcb); F_____;
+/** 1111 1101 0000 a101 srca srcb maclo %1, %2, %0 */
+ ID(maclo); DR(a+32); SR(srca); S2R(srcb); F_____;
-/** 1111 1101 0001 0111 0000 rsrc mvtachi %1 */
- ID(mvtachi); SR(rsrc); F_____;
+/** 1111 1101 0001 0111 a000 rsrc mvtachi %1, %0 */
+ ID(mvtachi); DR(a+32); SR(rsrc); F_____;
-/** 1111 1101 0001 0111 0001 rsrc mvtaclo %1 */
- ID(mvtaclo); SR(rsrc); F_____;
+/** 1111 1101 0001 0111 a001 rsrc mvtaclo %1, %0 */
+ ID(mvtaclo); DR(a+32); SR(rsrc); F_____;
-/** 1111 1101 0001 1111 0000 rdst mvfachi %0 */
- ID(mvfachi); DR(rdst); F_____;
+/** 1111 1101 0001 111i a m00 rdst mvfachi #%2, %1, %0 */
+ ID(mvfachi); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
-/** 1111 1101 0001 1111 0010 rdst mvfacmi %0 */
- ID(mvfacmi); DR(rdst); F_____;
+/** 1111 1101 0001 111i a m10 rdst mvfacmi #%2, %1, %0 */
+ ID(mvfacmi); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
-/** 1111 1101 0001 1111 0001 rdst mvfaclo %0 */
- ID(mvfaclo); DR(rdst); F_____;
+/** 1111 1101 0001 111i a m01 rdst mvfaclo #%2, %1, %0 */
+ ID(mvfaclo); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
-/** 1111 1101 0001 1000 000i 0000 racw #%1 */
- ID(racw); SC(i+1); F_____;
+/** 1111 1101 0001 1000 a00i 0000 racw #%1, %0 */
+ ID(racw); SC(i+1); DR(a+32); F_____;
/*----------------------------------------------------------------------*/
/* SAT */
@@ -1039,6 +1039,81 @@ rx_decode_opcode (unsigned long pc AU,
/** 1111 1100 1101 sz sd rdst cond sc%1%s %0 */
ID(sccnd); BWL(sz); DD (sd, rdst, sz); Scc(cond);
+/*----------------------------------------------------------------------*/
+/* RXv2 enhanced */
+
+/** 1111 1101 0010 0111 rdst rsrc movco %1, [%0] */
+ ID(mov); SR(rsrc); DR(rdst); F_____;
+
+/** 1111 1101 0010 1111 rsrc rdst movli [%1], %0 */
+ ID(mov); SR(rsrc); DR(rdst); F_____;
+
+/** 1111 1100 0100 1011 rsrc rdst stz %1, %0 */
+ ID(stcc); SR(rsrc); DR(rdst); S2cc(RXC_z);
+
+/** 1111 1100 0100 1111 rsrc rdst stnz %1, %0 */
+ ID(stcc); SR(rsrc); DR(rdst); S2cc(RXC_z);
+
+/** 1111 1101 0000 a111 srca srcb emaca %1, %2, %0 */
+ ID(emaca); DR(a+32); SR(srca); S2R(srcb); F_____;
+
+/** 1111 1101 0100 a111 srca srcb emsba %1, %2, %0 */
+ ID(emsba); DR(a+32); SR(srca); S2R(srcb); F_____;
+
+/** 1111 1101 0000 a011 srca srcb emula %1, %2, %0 */
+ ID(emula); DR(a+32); SR(srca); S2R(srcb); F_____;
+
+/** 1111 1101 0000 a110 srca srcb maclh %1, %2, %0 */
+ ID(maclh); DR(a+32); SR(srca); S2R(srcb); F_____;
+
+/** 1111 1101 0100 a100 srca srcb msbhi %1, %2, %0 */
+ ID(msbhi); DR(a+32); SR(srca); S2R(srcb); F_____;
+
+/** 1111 1101 0100 a110 srca srcb msblh %1, %2, %0 */
+ ID(msblh); DR(a+32); SR(srca); S2R(srcb); F_____;
+
+/** 1111 1101 0100 a101 srca srcb msblo %1, %2, %0 */
+ ID(msblo); DR(a+32); SR(srca); S2R(srcb); F_____;
+
+/** 1111 1101 0000 a010 srca srcb mullh %1, %2, %0 */
+ ID(mullh); DR(a+32); SR(srca); S2R(srcb); F_____;
+
+/** 1111 1101 0001 111i a m11 rdst mvfacgu #%2, %1, %0 */
+ ID(mvfacgu); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
+
+/** 1111 1101 0001 0111 a011 rdst mvtacgu %0, %1 */
+ ID(mvtacgu); SR(a+32); DR(rdst); F_____;
+
+/** 1111 1101 0001 1001 a00i 0000 racl #%1, %0 */
+ ID(racl); SC(i+1); DR(a+32); F_____;
+
+/** 1111 1101 0001 1001 a10i 0000 rdacl #%1, %0 */
+ ID(rdacl); SC(i+1); DR(a+32); F_____;
+
+/** 1111 1101 0001 1000 a10i 0000 rdacw #%1, %0 */
+ ID(rdacw); SC(i+1); DR(a+32); F_____;
+
+/** 1111 1111 1010 rdst srca srcb fadd %2, %1, %0 */
+ ID(fadd); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
+
+/** 1111 1111 1000 rdst srca srcb fsub %2, %1, %0 */
+ ID(fsub); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
+
+/** 1111 1111 1011 rdst srca srcb fmul %2, %1, %0 */
+ ID(fmul); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
+
+/** 1111 1100 1010 00sd rsrc rdst fsqrt %1%S1, %0 */
+ ID(fsqrt); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
+
+/** 1111 1100 1010 01sd rsrc rdst ftou %1%S1, %0 */
+ ID(ftou); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
+
+/** 1111 1100 0101 01sd rsrc rdst utof %1%S1, %0 */
+ ID(utof); DR (rdst); SP(sd, rsrc); F__SZ_;
+
+/** 0000 0110 mx10 00sd 0001 0101 rsrc rdst utof %1%S1, %0 */
+ ID(utof); DR (rdst); SPm(sd, rsrc, mx); F__SZ_;
+
/** */
return rx->n_bytes;