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author | Nelson Chu <nelson.chu@sifive.com> | 2021-11-17 18:46:11 +0800 |
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committer | Nelson Chu <nelson.chu@sifive.com> | 2021-11-17 20:18:11 +0800 |
commit | 65e4a99a26452d99d586f6e5a0c43e24348a5125 (patch) | |
tree | 92a3eca7a03c023591d661a6869135e3bf1522f1 /opcodes/riscv-dis.c | |
parent | 486f9e20e037f1eea2dce98dc393db60df5feef3 (diff) | |
download | gdb-65e4a99a26452d99d586f6e5a0c43e24348a5125.zip gdb-65e4a99a26452d99d586f6e5a0c43e24348a5125.tar.gz gdb-65e4a99a26452d99d586f6e5a0c43e24348a5125.tar.bz2 |
RISC-V: Support rvv extension with released version 1.0.
2021-11-17 Jim Wilson <jimw@sifive.com>
Kito Cheng <kito.cheng@sifive.com>
Nelson Chu <nelson.chu@sifive.com>
This patch is porting from the following riscv github,
https://github.com/riscv/riscv-binutils-gdb/tree/rvv-1.0.x
And here is the vector spec,
https://github.com/riscv/riscv-v-spec
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Added imply rules
of v, zve and zvl extensions.
(riscv_supported_std_ext): Updated verison of v to 1.0.
(riscv_supported_std_z_ext): Added zve and zvl extensions.
(riscv_parse_check_conflicts): The zvl extensions need to
enable either v or zve extension.
(riscv_multi_subset_supports): Check the subset list to know
if the INSN_CLASS_V and INSN_CLASS_ZVEF instructions are supported.
gas/
* config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_V.
(enum reg_class): Added RCLASS_VECR and RCLASS_VECM.
(validate_riscv_insn): Check whether the rvv operands are valid.
(md_begin): Initialize register hash for rvv registers.
(macro_build): Added rvv operands when expanding rvv pseudoes.
(vector_macro): Expand rvv macros into one or more instructions.
(macro): Likewise.
(my_getVsetvliExpression): Similar to my_getVsetvliExpression,
but used for parsing vsetvli operands.
(riscv_ip): Parse and encode rvv operands. Besides, The rvv loads
and stores with EEW 64 cannot be used when zve32x is enabled.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Updated -march
to rv32ifv_zkr.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg.s: Added rvv csr testcases.
* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/march-imply-v.d: New testcase.
* testsuite/gas/riscv/vector-insns-fail-zve32xf.d: Likewise.
* testsuite/gas/riscv/vector-insns-fail-zve32xf.l: Likewise.
* testsuite/gas/riscv/vector-insns-fail-zvl.d: Likewise.
* testsuite/gas/riscv/vector-insns-fail-zvl.l: Likewise.
* testsuite/gas/riscv/vector-insns-vmsgtvx.d: Likewise.
* testsuite/gas/riscv/vector-insns-vmsgtvx.s: Likewise.
* testsuite/gas/riscv/vector-insns-zero-imm.d: Likewise.
* testsuite/gas/riscv/vector-insns-zero-imm.s: Likewise.
* testsuite/gas/riscv/vector-insns.d: Likewise.
* testsuite/gas/riscv/vector-insns.s: Likewise.
include/
* opcode/riscv-opc.h: Defined mask/match encodings and csrs for rvv.
* opcode/riscv.h: Defined rvv immediate encodings and fields.
(enum riscv_insn_class): Added INSN_CLASS_V and INSN_CLASS_ZVEF.
(INSN_V_EEW64): Defined.
(M_VMSGE, M_VMSGEU): Added for the rvv pseudoes.
opcodes/
* riscv-dis.c (print_insn_args): Dump the rvv operands.
* riscv-opc.c (riscv_vecr_names_numeric): Defined rvv registers.
(riscv_vecm_names_numeric): Likewise.
(riscv_vsew): Likewise.
(riscv_vlmul): Likewise.
(riscv_vta): Likewise.
(riscv_vma): Likewise.
(match_vs1_eq_vs2): Added for rvv Vu operand.
(match_vd_eq_vs1_eq_vs2): Added for rvv Vv operand.
(riscv_opcodes): Added rvv v1.0 instructions.
Diffstat (limited to 'opcodes/riscv-dis.c')
-rw-r--r-- | opcodes/riscv-dis.c | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 86e2e5a..fac80b4 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -291,6 +291,73 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info } break; + case 'V': /* RVV */ + switch (*++oparg) + { + case 'd': + case 'f': + print (info->stream, "%s", + riscv_vecr_names_numeric[EXTRACT_OPERAND (VD, l)]); + break; + case 'e': + if (!EXTRACT_OPERAND (VWD, l)) + print (info->stream, "%s", riscv_gpr_names[0]); + else + print (info->stream, "%s", + riscv_vecr_names_numeric[EXTRACT_OPERAND (VD, l)]); + break; + case 's': + print (info->stream, "%s", + riscv_vecr_names_numeric[EXTRACT_OPERAND (VS1, l)]); + break; + case 't': + case 'u': /* VS1 == VS2 already verified at this point. */ + case 'v': /* VD == VS1 == VS2 already verified at this point. */ + print (info->stream, "%s", + riscv_vecr_names_numeric[EXTRACT_OPERAND (VS2, l)]); + break; + case '0': + print (info->stream, "%s", riscv_vecr_names_numeric[0]); + break; + case 'b': + case 'c': + { + int imm = (*oparg == 'b') ? EXTRACT_RVV_VB_IMM (l) + : EXTRACT_RVV_VC_IMM (l); + unsigned int imm_vlmul = EXTRACT_OPERAND (VLMUL, imm); + unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, imm); + unsigned int imm_vta = EXTRACT_OPERAND (VTA, imm); + unsigned int imm_vma = EXTRACT_OPERAND (VMA, imm); + unsigned int imm_vtype_res = EXTRACT_OPERAND (VTYPE_RES, imm); + + if (imm_vsew < ARRAY_SIZE (riscv_vsew) + && imm_vlmul < ARRAY_SIZE (riscv_vlmul) + && imm_vta < ARRAY_SIZE (riscv_vta) + && imm_vma < ARRAY_SIZE (riscv_vma) + && !imm_vtype_res) + print (info->stream, "%s,%s,%s,%s", riscv_vsew[imm_vsew], + riscv_vlmul[imm_vlmul], riscv_vta[imm_vta], + riscv_vma[imm_vma]); + else + print (info->stream, "%d", imm); + } + break; + case 'i': + print (info->stream, "%d", (int)EXTRACT_RVV_VI_IMM (l)); + break; + case 'j': + print (info->stream, "%d", (int)EXTRACT_RVV_VI_UIMM (l)); + break; + case 'k': + print (info->stream, "%d", (int)EXTRACT_RVV_OFFSET (l)); + break; + case 'm': + if (! EXTRACT_OPERAND (VMASK, l)) + print (info->stream, ",%s", riscv_vecm_names_numeric[0]); + break; + } + break; + case ',': case '(': case ')': |