aboutsummaryrefslogtreecommitdiff
path: root/opcodes/mips-dis.c
diff options
context:
space:
mode:
authorThiemo Seufer <ths@networkno.de>2006-05-04 10:47:05 +0000
committerThiemo Seufer <ths@networkno.de>2006-05-04 10:47:05 +0000
commit39a7806daee10b8020ce7be18e54cab69c9e699f (patch)
treee0e709f3dc36ebd5135bd8a533c7f16a44ec5a3c /opcodes/mips-dis.c
parent9578239d3edd0341cca6686bdf89ba9f5a1cd9f7 (diff)
downloadgdb-39a7806daee10b8020ce7be18e54cab69c9e699f.zip
gdb-39a7806daee10b8020ce7be18e54cab69c9e699f.tar.gz
gdb-39a7806daee10b8020ce7be18e54cab69c9e699f.tar.bz2
[ gas/testsuite/ChangeLog ]
2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> * gas/mips/mips.exp: Run mips32-dsp tests only for mips32r2. * gas/mips/set-arch.d: Adjust according to opcode table changes. [ include/opcode/ChangeLog ] 2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> * mips.h: Add INSN_SMARTMIPS define. [ opcodes/ChangeLog ] 2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> * mips-dis.c (mips_arch_choices): Add smartmips instruction decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to MIPS64R2. * mips-opc.c: fix random typos in comments. (INSN_SMARTMIPS): New defines. (mips_builtin_opcodes): Add paired single support for MIPS32R2. Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd, flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the FP_S and FP_D flags to denote single and double register accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards. Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1 for MIPS32R2. Add SmartMIPS instructions. Add two-argument variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to release 2 ISAs. * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
Diffstat (limited to 'opcodes/mips-dis.c')
-rw-r--r--opcodes/mips-dis.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 59e1824..64a1fa1 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -394,26 +394,28 @@ const struct mips_arch_choice mips_arch_choices[] =
MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
page 1. */
{ "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
- ISA_MIPS32 | INSN_MIPS16 | INSN_DSP,
+ ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
mips_cp0_names_mips3264,
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
mips_hwr_names_numeric },
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
- ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP | INSN_MT,
+ (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_MIPS3D
+ | INSN_MT),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
/* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
{ "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
- ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP,
+ ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
mips_cp0_names_mips3264,
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
mips_hwr_names_numeric },
{ "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
- ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP,
+ (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP
+ | INSN_MT | INSN_MDMX),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },