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authorDJ Delorie <dj@redhat.com>2005-10-25 18:52:02 +0000
committerDJ Delorie <dj@redhat.com>2005-10-25 18:52:02 +0000
commit92e0a9414cfe5bc3f1ec72a2ff1fae5b8838845b (patch)
tree6949f9422509b84b7b4664a87e2a03e082698fbb /opcodes/m32c-desc.c
parentb7b8fb1dfa651aa037c5b22df89e4356dfabd9e0 (diff)
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* m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by
making one a macro of the other. * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.c: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate.
Diffstat (limited to 'opcodes/m32c-desc.c')
-rw-r--r--opcodes/m32c-desc.c26
1 files changed, 2 insertions, 24 deletions
diff --git a/opcodes/m32c-desc.c b/opcodes/m32c-desc.c
index 01c5215..d75c908 100644
--- a/opcodes/m32c-desc.c
+++ b/opcodes/m32c-desc.c
@@ -1422,10 +1422,6 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
{ "A1", M32C_OPERAND_A1, HW_H_A1, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-/* A1A0: a1a0 */
- { "A1A0", M32C_OPERAND_A1A0, HW_H_AR_SI, 0, 0,
- { 0, { (const PTR) 0 } },
- { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
/* sb: SB register */
{ "sb", M32C_OPERAND_SB, HW_H_SB, 0, 0,
{ 0, { (const PTR) 0 } },
@@ -2046,24 +2042,6 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
/* src32-24-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
/* src32-24-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
/* src32-24-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
-/* dsp20-16-u20-QI: m16c dsp:20 absolute destination QI */
-/* dsp20-16-u20-A0-QI: m16c dsp:20[A0] relative destination QI */
-/* dsp20-16-A1A0-QI: m16c [A1A0] relative destination QI */
-/* dsp20-24-u20-QI: m16c dsp:20 absolute destination QI */
-/* dsp20-24-u20-A0-QI: m16c dsp:20[A0] relative destination QI */
-/* dsp20-24-A1A0-QI: m16c [A1A0] relative destination QI */
-/* dsp20-32-u20-QI: m16c dsp:20 absolute destination QI */
-/* dsp20-32-u20-A0-QI: m16c dsp:20[A0] relative destination QI */
-/* dsp20-32-A1A0-QI: m16c [A1A0] relative destination QI */
-/* dsp20-16-u20-HI: m16c dsp:20 absolute destination HI */
-/* dsp20-16-u20-A0-HI: m16c dsp:20[A0] relative destination HI */
-/* dsp20-16-A1A0-HI: m16c [A1A0] relative destination HI */
-/* dsp20-24-u20-HI: m16c dsp:20 absolute destination HI */
-/* dsp20-24-u20-A0-HI: m16c dsp:20[A0] relative destination HI */
-/* dsp20-24-A1A0-HI: m16c [A1A0] relative destination HI */
-/* dsp20-32-u20-HI: m16c dsp:20 absolute destination HI */
-/* dsp20-32-u20-A0-HI: m16c dsp:20[A0] relative destination HI */
-/* dsp20-32-A1A0-HI: m16c [A1A0] relative destination HI */
/* src16-16-16-absolute-QI: m16c absolute address QI */
/* src16-16-16-absolute-HI: m16c absolute address HI */
/* src32-16-16-absolute-Unprefixed-QI: m32c absolute address QI */
@@ -61854,9 +61832,9 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
M32C_INSN_ABS16_B_16_DST16_16_16_ABSOLUTE_QI, "abs16.b-16-dst16-16-16-absolute-QI", "abs.b", 32,
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
},
-/* add${size}$Q #${Imm-12-s4},sp */
+/* add.w$Q #${Imm-12-s4},sp */
{
- M32C_INSN_ADD16_Q_SP, "add16-Q-sp", "add", 16,
+ M32C_INSN_ADD16_WQ_SP, "add16-wQ-sp", "add.w", 16,
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
},
/* add.b$G #${Imm-16-QI},sp */