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author | Jan Beulich <jbeulich@suse.com> | 2023-12-15 12:40:00 +0100 |
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committer | Jan Beulich <jbeulich@suse.com> | 2023-12-15 12:40:00 +0100 |
commit | df5a4840c4088f3fca93ba77db76960cea7b66c4 (patch) | |
tree | 4fe00658f26d246b110d477b11d4f0c59c3a303b /opcodes/i386-tbl.h | |
parent | 35266cb139697e00ee993118aa621fdac17e3f6e (diff) | |
download | gdb-df5a4840c4088f3fca93ba77db76960cea7b66c4.zip gdb-df5a4840c4088f3fca93ba77db76960cea7b66c4.tar.gz gdb-df5a4840c4088f3fca93ba77db76960cea7b66c4.tar.bz2 |
revert "x86: allow 32-bit reg to be used with U{RD,WR}MSR"
This reverts commit 1f865bae65db9588f6994c02a92355bfb4e3d955. The
specification is going to by updated in a way rendering this change
wrong.
Diffstat (limited to 'opcodes/i386-tbl.h')
-rw-r--r-- | opcodes/i386-tbl.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 024d194..c4347d4 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -35866,7 +35866,7 @@ static const insn_template i386_optab[] = 0, 0, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { 98, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } } }, @@ -35886,7 +35886,7 @@ static const insn_template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }, - { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_uwrmsr, 0xf8, 2, SPACE_VEXMAP7, 0, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, |