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| author | Jan Beulich <jbeulich@novell.com> | 2018-09-13 11:07:07 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2018-09-13 11:07:07 +0200 |
| commit | dbbc8b7e629fa666affd9a3f475d0bf6e5264677 (patch) | |
| tree | 316472083e52276cc78cdaf84062a83c2cb8489e /opcodes/i386-opc.h | |
| parent | efb192033ad82855bcfab207f8494e8b1f3e243b (diff) | |
| download | gdb-dbbc8b7e629fa666affd9a3f475d0bf6e5264677.zip gdb-dbbc8b7e629fa666affd9a3f475d0bf6e5264677.tar.gz gdb-dbbc8b7e629fa666affd9a3f475d0bf6e5264677.tar.bz2 | |
x86: use D attribute also for SIMD templates
Various moves come in load and store forms, and just like on the GPR
and FPU sides there would better be only one pattern. In some cases this
is not feasible because the opcodes are too different, but quite a few
cases follow a similar standard scheme. Introduce Opcode_SIMD_FloatD and
Opcode_SIMD_IntD, generalize handling in operand_size_match() (reverse
operand handling there simply needs to match "straight" operand one),
and fix a long standing, but so far only latent bug with when to zap
found_reverse_match.
Also once again drop IgnoreSize where pointlessly applied to templates
touched anyway as well as *word when redundant with Reg*.
Diffstat (limited to 'opcodes/i386-opc.h')
| -rw-r--r-- | opcodes/i386-opc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 3d0dd44..a7f0ba2 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -861,6 +861,8 @@ typedef struct insn_template unset if Regmem --> Reg. */ #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ #define Opcode_FloatD 0x400 /* Direction bit for float insns. */ +#define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */ +#define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */ /* extension_opcode is the 3 bit extension for group <n> insns. This field is also used to store the 8-bit opcode suffix for the |