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| author | H.J. Lu <hjl.tools@gmail.com> | 2020-02-10 08:37:22 -0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2020-02-10 08:37:36 -0800 |
| commit | 4b5aaf5f6992319c2c72e080a1a55842640b8732 (patch) | |
| tree | b75a8c08300589ff7d3f6fb820be4d56fe8a1f54 /opcodes/i386-opc.h | |
| parent | 3a5d12fbb4f7888525978f9fba46b977afabe391 (diff) | |
| download | gdb-4b5aaf5f6992319c2c72e080a1a55842640b8732.zip gdb-4b5aaf5f6992319c2c72e080a1a55842640b8732.tar.gz gdb-4b5aaf5f6992319c2c72e080a1a55842640b8732.tar.bz2 | |
x86: Accept Intel64 only instruction by default
Commit d835a58baae720 disabled sysenter/sysenter in 64-bit mode by
default. By default, assembler should accept common, Intel64 only
and AMD64 ISAs since there are no conflicts.
gas/
PR gas/25516
* config/tc-i386.c (intel64): Renamed to ...
(isa64): This.
(match_template): Accept Intel64 only instruction by default.
(i386_displacement): Updated.
(md_parse_option): Updated.
* c-i386.texi: Update -mamd64/-mintel64 documentation.
* testsuite/gas/i386/i386.exp: Run x86-64-sysenter. Pass
-mamd64 to x86-64-sysenter-amd.
* testsuite/gas/i386/x86-64-sysenter.d: New file.
opcodes/
PR gas/25516
* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
with ISA64.
* i386-opc.h (AMD64): Removed.
(Intel64): Likewose.
(AMD64): New.
(INTEL64): Likewise.
(INTEL64ONLY): Likewise.
(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
* i386-opc.tbl (Amd64): New.
(Intel64): Likewise.
(Intel64Only): Likewise.
Replace AMD64 with Amd64. Update sysenter/sysenter with
Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes/i386-opc.h')
| -rw-r--r-- | opcodes/i386-opc.h | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index cdc7cb2..ecd441e 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -638,10 +638,16 @@ enum ATTSyntax, /* Intel syntax. */ IntelSyntax, - /* AMD64. */ - AMD64, - /* Intel64. */ - Intel64, + /* ISA64: Don't change the order without other code adjustments. + 0: Common to AMD64 and Intel64. + 1: AMD64. + 2: Intel64. + 3: Only in Intel64. + */ +#define AMD64 1 +#define INTEL64 2 +#define INTEL64ONLY 3 + ISA64, /* The last bitfield in i386_opcode_modifier. */ Opcode_Modifier_Num }; @@ -705,8 +711,7 @@ typedef struct i386_opcode_modifier unsigned int attmnemonic:1; unsigned int attsyntax:1; unsigned int intelsyntax:1; - unsigned int amd64:1; - unsigned int intel64:1; + unsigned int isa64:2; } i386_opcode_modifier; /* Operand classes. */ |