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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:16 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:16 +0100 |
| commit | ce623e7aa486d1330c9a4529c77a302d2fdcb801 (patch) | |
| tree | 0eb2f066a02a0cd040e95eeb05c40a4aea975cec /opcodes/aarch64-asm.c | |
| parent | c04965ec7d8819448f7d7b48cee9fa6567e67455 (diff) | |
| download | gdb-ce623e7aa486d1330c9a4529c77a302d2fdcb801.zip gdb-ce623e7aa486d1330c9a4529c77a302d2fdcb801.tar.gz gdb-ce623e7aa486d1330c9a4529c77a302d2fdcb801.tar.bz2 | |
aarch64: Add the SME2 saturating conversion instructions
There are two instruction formats here:
- SQCVT, SQCVTU and UQCVT, which operate on lists of two or
four registers.
- SQCVTN, SQCVTUN and UQCVTN, which operate on lists of
four registers.
Diffstat (limited to 'opcodes/aarch64-asm.c')
| -rw-r--r-- | opcodes/aarch64-asm.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index b1d2d58..5f2e510 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1970,6 +1970,11 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) aarch64_get_variant (inst) + 1, 0); break; + case sme_sz_23: + insert_field (FLD_SME_sz_23, &inst->value, + aarch64_get_variant (inst), 0); + break; + case sve_cpy: insert_fields (&inst->value, aarch64_get_variant (inst), 0, 2, FLD_SVE_M_14, FLD_size); |