RISC-V: Merge ELF attribute for ld.

	2019-01-16  Kito Cheng  <kito@andestech.com>
		    Nelson Chu  <nelson@andestech.com>

	bfd/
	* elfnn-riscv.c (in_subsets): New.
	(out_subsets): Likewise.
	(merged_subsets): Likewise.
	(riscv_std_ext_p): Likewise.
	(riscv_non_std_ext_p): Likewise.
	(riscv_std_sv_ext_p): Likewise.
	(riscv_non_std_sv_ext_p): Likewise.
	(riscv_version_mismatch): Likewise.
	(riscv_i_or_e_p): Likewise.
	(riscv_merge_std_ext): Likewise.
	(riscv_merge_non_std_and_sv_ext): Likewise.
	(riscv_merge_arch_attr_info): Likewise.
	(riscv_merge_attributes): Likewise.
	(_bfd_riscv_elf_merge_private_bfd_data): Merge attribute.
	ld/
	* testsuite/ld-elf/orphan-region.d: XFAIL for RISC-V, because add new
	section.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Add new tests.
	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: New test.
	* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-01a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-01b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align-a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align-b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align-failed-a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align-failed-b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align-failed.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-01a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-01b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-02a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-02b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-03a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-03b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-04a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-04b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-05a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-05b.s: Likewise.

38 files changed, 189 insertions, 0 deletions

diff --git a/ld/ChangeLog b/ld/ChangeLog
index ba5b0e9..cde82e3 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,45 @@
+2019-01-16  Kito Cheng  <kito@andestech.com>
+
+	* testsuite/ld-elf/orphan-region.d: XFAIL for RISC-V, because add new
+	section.
+	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Add new tests.
+	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: New test.
+	* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-arch-failed-01a.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-arch-failed-01b.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-stack-align-a.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-stack-align-b.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-stack-align-failed-a.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-stack-align-failed-b.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-stack-align-failed.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-01a.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-01b.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-02a.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-02b.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-03a.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-03b.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-04a.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-04b.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-05a.s: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-05b.s: Likewise.
+
 2019-01-14  Maamoun Tarsha  <maamountk@hotmail.com>
 
 	PR 20113
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
new file mode 100644
index 0000000..5baaba4
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
@@ -0,0 +1,9 @@
+#source: attr-merge-arch-01a.s
+#source: attr-merge-arch-01b.s
+#as:
+#ld: -r -melf32lriscv
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p0_m2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
new file mode 100644
index 0000000..acc98a5
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
@@ -0,0 +1 @@
+	.attribute arch, "rv32i2p0_m2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
new file mode 100644
index 0000000..acc98a5
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
@@ -0,0 +1 @@
+	.attribute arch, "rv32i2p0_m2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
new file mode 100644
index 0000000..a7d79a1
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
@@ -0,0 +1,9 @@
+#source: attr-merge-arch-02a.s
+#source: attr-merge-arch-02b.s
+#as:
+#ld: -r -melf32lriscv
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p0_m2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
new file mode 100644
index 0000000..acc98a5
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
@@ -0,0 +1 @@
+	.attribute arch, "rv32i2p0_m2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s
new file mode 100644
index 0000000..65d0fef
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s
@@ -0,0 +1 @@
+	.attribute arch, "rv32i2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
new file mode 100644
index 0000000..d46dee8
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
@@ -0,0 +1,9 @@
+#source: attr-merge-arch-03a.s
+#source: attr-merge-arch-03b.s
+#as:
+#ld: -r -melf32lriscv
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
new file mode 100644
index 0000000..b86cc55
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
@@ -0,0 +1 @@
+	.attribute arch, "rv32i2p0_m2p0_xfoo2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s
new file mode 100644
index 0000000..376e373
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s
@@ -0,0 +1 @@
+	.attribute arch, "rv32i2p0_xbar2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d
new file mode 100644
index 0000000..564687d
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d
@@ -0,0 +1,5 @@
+#source: attr-merge-arch-failed-01a.s
+#source: attr-merge-arch-failed-01b.s
+#as: -march-attr
+#ld: -r -melf32lriscv
+#error: Mis-matched ISA version for 'm' exetension. 3.0 vs 2.0
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01a.s
new file mode 100644
index 0000000..acc98a5
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01a.s
@@ -0,0 +1 @@
+	.attribute arch, "rv32i2p0_m2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01b.s
new file mode 100644
index 0000000..c9a590a
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01b.s
@@ -0,0 +1 @@
+	.attribute arch, "rv32i2p0_m3p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s
new file mode 100644
index 0000000..1ad9500
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s
@@ -0,0 +1,3 @@
+	.attribute priv_spec, 1
+	.attribute priv_spec_minor, 2
+	.attribute priv_spec_revision, 3
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s
new file mode 100644
index 0000000..1ad9500
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s
@@ -0,0 +1,3 @@
+	.attribute priv_spec, 1
+	.attribute priv_spec_minor, 2
+	.attribute priv_spec_revision, 3
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d
new file mode 100644
index 0000000..dc4c4e0
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d
@@ -0,0 +1,12 @@
+#source: attr-merge-priv-spec-a.s
+#source: attr-merge-priv-spec-b.s
+#as: -march-attr
+#ld: -r
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+  Tag_RISCV_priv_spec: 1
+  Tag_RISCV_priv_spec_minor: 2
+  Tag_RISCV_priv_spec_revision: 3
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align-a.s b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align-a.s
new file mode 100644
index 0000000..273d829
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align-a.s
@@ -0,0 +1 @@
+	.attribute stack_align, 16
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align-b.s b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align-b.s
new file mode 100644
index 0000000..273d829
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align-b.s
@@ -0,0 +1 @@
+	.attribute stack_align, 16
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align-failed-a.s b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align-failed-a.s
new file mode 100644
index 0000000..273d829
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align-failed-a.s
@@ -0,0 +1 @@
+	.attribute stack_align, 16
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align-failed-b.s b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align-failed-b.s
new file mode 100644
index 0000000..73b7238
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align-failed-b.s
@@ -0,0 +1 @@
+	.attribute stack_align, 4
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align-failed.d b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align-failed.d
new file mode 100644
index 0000000..917f06e
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align-failed.d
@@ -0,0 +1,5 @@
+#source: attr-merge-stack-align-failed-a.s
+#source: attr-merge-stack-align-failed-b.s
+#as:
+#ld: -r
+#error: .*use 4-byte stack aligned but the output use 16-byte stack aligned.
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
new file mode 100644
index 0000000..7a5bc81
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
@@ -0,0 +1,10 @@
+#source: attr-merge-stack-align-a.s
+#source: attr-merge-stack-align-b.s
+#as: -march-attr
+#ld: -r
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_stack_align: 16-bytes
+  Tag_RISCV_arch: [a-zA-Z0-9_\"].*
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
new file mode 100644
index 0000000..1039930
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
@@ -0,0 +1,10 @@
+#source: attr-merge-strict-align-01a.s
+#source: attr-merge-strict-align-01b.s
+#as: -march-attr
+#ld: -r
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+  Tag_RISCV_unaligned_access: Unaligned access
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01a.s b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01a.s
new file mode 100644
index 0000000..55ffc07
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01a.s
@@ -0,0 +1 @@
+	.attribute unaligned_access, 1
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01b.s b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01b.s
new file mode 100644
index 0000000..55ffc07
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01b.s
@@ -0,0 +1 @@
+	.attribute unaligned_access, 1
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
new file mode 100644
index 0000000..12ca1c4
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
@@ -0,0 +1,10 @@
+#source: attr-merge-strict-align-02a.s
+#source: attr-merge-strict-align-02b.s
+#as: -march-attr
+#ld: -r
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+  Tag_RISCV_unaligned_access: Unaligned access
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02a.s b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02a.s
new file mode 100644
index 0000000..55ffc07
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02a.s
@@ -0,0 +1 @@
+	.attribute unaligned_access, 1
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02b.s b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02b.s
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02b.s
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
new file mode 100644
index 0000000..e41351d
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
@@ -0,0 +1,10 @@
+#source: attr-merge-strict-align-03a.s
+#source: attr-merge-strict-align-03b.s
+#as: -march-attr
+#ld: -r
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+  Tag_RISCV_unaligned_access: Unaligned access
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03a.s b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03a.s
new file mode 100644
index 0000000..55ffc07
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03a.s
@@ -0,0 +1 @@
+	.attribute unaligned_access, 1
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03b.s b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03b.s
new file mode 100644
index 0000000..a88149e
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03b.s
@@ -0,0 +1 @@
+	.attribute unaligned_access, 0
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
new file mode 100644
index 0000000..ac2a766
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
@@ -0,0 +1,9 @@
+#source: attr-merge-strict-align-04a.s
+#source: attr-merge-strict-align-04b.s
+#as: -march-attr
+#ld: -r
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: [a-zA-Z0-9_\"].*
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04a.s b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04a.s
new file mode 100644
index 0000000..a88149e
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04a.s
@@ -0,0 +1 @@
+	.attribute unaligned_access, 0
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04b.s b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04b.s
new file mode 100644
index 0000000..a88149e
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04b.s
@@ -0,0 +1 @@
+	.attribute unaligned_access, 0
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
new file mode 100644
index 0000000..608c05e
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
@@ -0,0 +1,10 @@
+#source: attr-merge-strict-align-05a.s
+#source: attr-merge-strict-align-05b.s
+#as: -march-attr
+#ld: -r
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+  Tag_RISCV_unaligned_access: Unaligned access
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05a.s b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05a.s
new file mode 100644
index 0000000..55ffc07
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05a.s
@@ -0,0 +1 @@
+	.attribute unaligned_access, 1
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05b.s b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05b.s
new file mode 100644
index 0000000..55ffc07
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05b.s
@@ -0,0 +1 @@
+	.attribute unaligned_access, 1
diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index 0bedd5e..bce7bfe 100644
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -24,6 +24,18 @@ if [istarget "riscv*-*-*"] {
     run_dump_test "disas-jalr"
     run_dump_test "pcrel-lo-addend"
     run_dump_test "pcrel-lo-addend-2"
+    run_dump_test "attr-merge-arch-01"
+    run_dump_test "attr-merge-arch-02"
+    run_dump_test "attr-merge-arch-03"
+    run_dump_test "attr-merge-strict-align-01"
+    run_dump_test "attr-merge-strict-align-02"
+    run_dump_test "attr-merge-strict-align-03"
+    run_dump_test "attr-merge-strict-align-04"
+    run_dump_test "attr-merge-strict-align-05"
+    run_dump_test "attr-merge-stack-align"
+    run_dump_test "attr-merge-priv-spec"
+    run_dump_test "attr-merge-arch-failed-01"
+    run_dump_test "attr-merge-stack-align-failed"
     run_ld_link_tests {
 	{ "Weak reference 32" "-T weakref.ld -melf32lriscv" ""
 	    "-march=rv32i -mabi=ilp32" {weakref32.s}