* elf32-sh.c (tpoff): New.

	(struct elf_sh_dyn_relocs): Remove tls_tpoff32.
	(WILL_CALL_FINISH_DYNAMIC_SYMBOL): Pass SHARED instead of INFO.
        (allocate_dynrelocs): Don't make unnecessary dynamic TLS
	relocations.  Adjust WILL_CALL_FINISH_DYNAMIC_SYMBOL uses.
        (sh_elf_relocate_section): Likewise. Remove unnecessary tests.
	(dtpoff_base): Fix wrong indentation.
	(sh_elf_check_relocs): Don't set DF_STATIC_TLS flag with non-TLS
	relocations.  Don't set tls_tpoff32 flag.  Don't make unnecessary
	R_SH_TLS_TPOFF32 relocations.

	* ld-sh/tlsbin-1.d, ld-sh/tlsbin-2.d, ld-sh/tlsbin-3.d,
	ld-sh/tlstpoff-1.d, ld-sh/tlstpoff-2.d: Update for removing
	unnecessary TLS relocs.

6 files changed, 53 insertions, 54 deletions

diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index 8d2c9de..b7438ef 100644
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2003-04-23  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/tlsbin-1.d, ld-sh/tlsbin-2.d, ld-sh/tlsbin-3.d,
+	ld-sh/tlstpoff-1.d, ld-sh/tlstpoff-2.d: Update for removing
+	unnecessary TLS relocs.
+
 2003-04-23  J"orn Rennecke <joern.rennecke@superh.com>
 
 	* ld-sh/sh64/crange3-cmpct.rd (Machine): Change to refer to SuperH.
diff --git a/ld/testsuite/ld-sh/tlsbin-1.d b/ld/testsuite/ld-sh/tlsbin-1.d
index 58acf5c..9f6d84f 100644
--- a/ld/testsuite/ld-sh/tlsbin-1.d
+++ b/ld/testsuite/ld-sh/tlsbin-1.d
@@ -54,7 +54,7 @@ Disassembly of section \.text:
   401052:	09 00       	nop	
   401054:	09 00       	nop	
   401056:	09 00       	nop	
-  401058:	03 d4       	mov\.l	401068 <fn2\+0x68>,r4	! 0x0
+  401058:	03 d4       	mov\.l	401068 <fn2\+0x68>,r4	! 0x8
   40105a:	12 00       	stc	gbr,r0
   40105c:	4c 30       	add	r4,r0
   40105e:	09 00       	nop	
@@ -62,7 +62,7 @@ Disassembly of section \.text:
   401062:	09 00       	nop	
   401064:	04 a0       	bra	401070 <fn2\+0x70>
   401066:	09 00       	nop	
-  401068:	00 00       	.*[ 	]*.*
+  401068:	08 00       	.*[ 	]*.*
   40106a:	00 00       	.*[ 	]*.*
   40106c:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
   40106e:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
@@ -70,7 +70,7 @@ Disassembly of section \.text:
   401072:	09 00       	nop	
   401074:	09 00       	nop	
   401076:	09 00       	nop	
-  401078:	03 d4       	mov\.l	401088 <fn2\+0x88>,r4	! 0x0
+  401078:	03 d4       	mov\.l	401088 <fn2\+0x88>,r4	! 0x10
   40107a:	12 00       	stc	gbr,r0
   40107c:	4c 30       	add	r4,r0
   40107e:	09 00       	nop	
@@ -78,7 +78,7 @@ Disassembly of section \.text:
   401082:	09 00       	nop	
   401084:	04 a0       	bra	401090 <fn2\+0x90>
   401086:	09 00       	nop	
-  401088:	00 00       	.*[ 	]*.*
+  401088:	10 00       	.*[ 	]*.*
   40108a:	00 00       	.*[ 	]*.*
   40108c:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
   40108e:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
@@ -86,7 +86,7 @@ Disassembly of section \.text:
   401092:	09 00       	nop	
   401094:	09 00       	nop	
   401096:	09 00       	nop	
-  401098:	03 d4       	mov\.l	4010a8 <fn2\+0xa8>,r4	! 0x0
+  401098:	03 d4       	mov\.l	4010a8 <fn2\+0xa8>,r4	! 0x18
   40109a:	12 00       	stc	gbr,r0
   40109c:	4c 30       	add	r4,r0
   40109e:	09 00       	nop	
@@ -94,7 +94,7 @@ Disassembly of section \.text:
   4010a2:	09 00       	nop	
   4010a4:	04 a0       	bra	4010b0 <fn2\+0xb0>
   4010a6:	09 00       	nop	
-  4010a8:	00 00       	.*[ 	]*.*
+  4010a8:	18 00       	.*[ 	]*.*
   4010aa:	00 00       	.*[ 	]*.*
   4010ac:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
   4010ae:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
@@ -116,11 +116,11 @@ Disassembly of section \.text:
   4010ce:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
   4010d0:	09 00       	nop	
   4010d2:	09 00       	nop	
-  4010d4:	2c d1       	mov\.l	401188 <fn2\+0x188>,r1	! 0x0
+  4010d4:	2c d1       	mov\.l	401188 <fn2\+0x188>,r1	! 0x10
   4010d6:	0c 31       	add	r0,r1
   4010d8:	09 00       	nop	
   4010da:	09 00       	nop	
-  4010dc:	2b d2       	mov\.l	40118c <fn2\+0x18c>,r2	! 0x0
+  4010dc:	2b d2       	mov\.l	40118c <fn2\+0x18c>,r2	! 0x14
   4010de:	0c 32       	add	r0,r2
   4010e0:	09 00       	nop	
   4010e2:	09 00       	nop	
@@ -140,11 +140,11 @@ Disassembly of section \.text:
   4010fe:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
   401100:	09 00       	nop	
   401102:	09 00       	nop	
-  401104:	22 d1       	mov\.l	401190 <fn2\+0x190>,r1	! 0x0
+  401104:	22 d1       	mov\.l	401190 <fn2\+0x190>,r1	! 0x18
   401106:	0c 31       	add	r0,r1
   401108:	09 00       	nop	
   40110a:	09 00       	nop	
-  40110c:	21 d2       	mov\.l	401194 <fn2\+0x194>,r2	! 0x0
+  40110c:	21 d2       	mov\.l	401194 <fn2\+0x194>,r2	! 0x1c
   40110e:	0c 32       	add	r0,r2
   401110:	09 00       	nop	
   401112:	09 00       	nop	
@@ -174,25 +174,25 @@ Disassembly of section \.text:
   401142:	09 00       	nop	
   401144:	09 00       	nop	
   401146:	09 00       	nop	
-  401148:	02 d0       	mov\.l	401154 <fn2\+0x154>,r0	! 0x0
+  401148:	02 d0       	mov\.l	401154 <fn2\+0x154>,r0	! 0x8
   40114a:	12 01       	stc	gbr,r1
   40114c:	09 00       	nop	
   40114e:	03 a0       	bra	401158 <fn2\+0x158>
   401150:	0c 31       	add	r0,r1
   401152:	09 00       	nop	
-  401154:	00 00       	.*[ 	]*.*
+  401154:	08 00       	.*[ 	]*.*
   401156:	00 00       	.*[ 	]*.*
   401158:	09 00       	nop	
   40115a:	09 00       	nop	
   40115c:	09 00       	nop	
   40115e:	09 00       	nop	
-  401160:	02 d0       	mov\.l	40116c <fn2\+0x16c>,r0	! 0x0
+  401160:	02 d0       	mov\.l	40116c <fn2\+0x16c>,r0	! 0x18
   401162:	12 01       	stc	gbr,r1
   401164:	09 00       	nop	
   401166:	03 a0       	bra	401170 <fn2\+0x170>
   401168:	0c 31       	add	r0,r1
   40116a:	09 00       	nop	
-  40116c:	00 00       	.*[ 	]*.*
+  40116c:	18 00       	.*[ 	]*.*
   40116e:	00 00       	.*[ 	]*.*
   401170:	09 00       	nop	
   401172:	09 00       	nop	
@@ -206,6 +206,13 @@ Disassembly of section \.text:
   401182:	09 00       	nop	
   401184:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
   401186:	01 00       	.*[ 	]*.*
+  401188:	10 00       	.*[ 	]*.*
+  40118a:	00 00       	.*[ 	]*.*
+  40118c:	14 00       	.*[ 	]*.*
+  40118e:	00 00       	.*[ 	]*.*
+  401190:	18 00       	.*[ 	]*.*
+  401192:	00 00       	.*[ 	]*.*
+  401194:	1c 00       	.*[ 	]*.*
 	\.\.\.
 
 00402000 <_start>:
@@ -231,58 +238,58 @@ Disassembly of section \.text:
   402026:	09 00       	nop	
   402028:	09 00       	nop	
   40202a:	09 00       	nop	
-  40202c:	02 d0       	mov\.l	402038 <_start\+0x38>,r0	! 0x0
+  40202c:	02 d0       	mov\.l	402038 <_start\+0x38>,r0	! 0x20
   40202e:	12 01       	stc	gbr,r1
   402030:	09 00       	nop	
   402032:	03 a0       	bra	40203c <_start\+0x3c>
   402034:	0c 31       	add	r0,r1
   402036:	09 00       	nop	
-  402038:	00 00       	.*[ 	]*.*
+  402038:	20 00       	.*[ 	]*.*
   40203a:	00 00       	.*[ 	]*.*
   40203c:	09 00       	nop	
   40203e:	09 00       	nop	
   402040:	09 00       	nop	
   402042:	09 00       	nop	
-  402044:	02 d0       	mov\.l	402050 <_start\+0x50>,r0	! 0x0
+  402044:	02 d0       	mov\.l	402050 <_start\+0x50>,r0	! 0x2c
   402046:	12 01       	stc	gbr,r1
   402048:	09 00       	nop	
   40204a:	03 a0       	bra	402054 <_start\+0x54>
   40204c:	0c 31       	add	r0,r1
   40204e:	09 00       	nop	
-  402050:	00 00       	.*[ 	]*.*
+  402050:	2c 00       	.*[ 	]*.*
   402052:	00 00       	.*[ 	]*.*
   402054:	09 00       	nop	
   402056:	09 00       	nop	
   402058:	09 00       	nop	
   40205a:	09 00       	nop	
-  40205c:	02 d0       	mov\.l	402068 <_start\+0x68>,r0	! 0x0
+  40205c:	02 d0       	mov\.l	402068 <_start\+0x68>,r0	! 0x1c
   40205e:	12 01       	stc	gbr,r1
   402060:	09 00       	nop	
   402062:	03 a0       	bra	40206c <_start\+0x6c>
   402064:	0c 31       	add	r0,r1
   402066:	09 00       	nop	
-  402068:	00 00       	.*[ 	]*.*
+  402068:	1c 00       	.*[ 	]*.*
   40206a:	00 00       	.*[ 	]*.*
   40206c:	09 00       	nop	
   40206e:	09 00       	nop	
   402070:	09 00       	nop	
   402072:	09 00       	nop	
   402074:	12 01       	stc	gbr,r1
-  402076:	0c d0       	mov\.l	4020a8 <_start\+0xa8>,r0	! 0x0
+  402076:	0c d0       	mov\.l	4020a8 <_start\+0xa8>,r0	! 0x8
   402078:	1c 30       	add	r1,r0
   40207a:	09 00       	nop	
   40207c:	09 00       	nop	
   40207e:	09 00       	nop	
   402080:	09 00       	nop	
   402082:	12 01       	stc	gbr,r1
-  402084:	09 d0       	mov\.l	4020ac <_start\+0xac>,r0	! 0x0
+  402084:	09 d0       	mov\.l	4020ac <_start\+0xac>,r0	! 0x28
   402086:	1c 30       	add	r1,r0
   402088:	09 00       	nop	
   40208a:	09 00       	nop	
   40208c:	09 00       	nop	
   40208e:	09 00       	nop	
   402090:	12 01       	stc	gbr,r1
-  402092:	07 d0       	mov\.l	4020b0 <_start\+0xb0>,r0	! 0x0
+  402092:	07 d0       	mov\.l	4020b0 <_start\+0xb0>,r0	! 0x18
   402094:	1c 30       	add	r1,r0
   402096:	09 00       	nop	
   402098:	09 00       	nop	
@@ -293,4 +300,9 @@ Disassembly of section \.text:
   4020a2:	f6 6e       	mov\.l	@r15\+,r14
   4020a4:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
   4020a6:	01 00       	.*[ 	]*.*
+  4020a8:	08 00       	.*[ 	]*.*
+  4020aa:	00 00       	.*[ 	]*.*
+  4020ac:	28 00       	.*[ 	]*.*
+  4020ae:	00 00       	.*[ 	]*.*
+  4020b0:	18 00       	.*[ 	]*.*
 	\.\.\.
diff --git a/ld/testsuite/ld-sh/tlsbin-2.d b/ld/testsuite/ld-sh/tlsbin-2.d
index a010ea9..d84b102 100644
--- a/ld/testsuite/ld-sh/tlsbin-2.d
+++ b/ld/testsuite/ld-sh/tlsbin-2.d
@@ -23,7 +23,7 @@ Section Headers:
   \[11\] \.tbss +NOBITS +0+413018 [0-9a-f]+ 0+010 00 WAT  0   0  1
   \[12\] \.dynamic +DYNAMIC +0+413018 .*
 #...
-  \[[0-9a-f]+\] \.got +PROGBITS +0+4130c0 .*
+  \[[0-9a-f]+\] \.got +PROGBITS +0+4130b8 .*
   \[[0-9a-f]+\] \.sbss +.*
   \[[0-9a-f]+\] \.bss +.*
 #...
@@ -58,31 +58,16 @@ Program Headers:
    04 +\.tbss \.dynamic *
    05 +\.tdata \.tbss *
 
-Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 19 entries:
+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 4 entries:
  Offset +Info +Type +Sym\.Value +Sym\. Name \+ Addend
-0+401068  00000097 R_SH_TLS_TPOFF32 +0+00
-0+401088  00000097 R_SH_TLS_TPOFF32 +0+08
-0+4010a8  00000097 R_SH_TLS_TPOFF32 +0+10
-0+401154  00000097 R_SH_TLS_TPOFF32 +0+00
-0+40116c  00000097 R_SH_TLS_TPOFF32 +0+10
-0+401188  00000097 R_SH_TLS_TPOFF32 +0+08
-0+40118c  00000097 R_SH_TLS_TPOFF32 +0+0c
-0+401190  00000097 R_SH_TLS_TPOFF32 +0+10
-0+401194  00000097 R_SH_TLS_TPOFF32 +0+14
-0+402038  00000097 R_SH_TLS_TPOFF32 +0+18
-0+402050  00000097 R_SH_TLS_TPOFF32 +0+24
-0+402068  00000097 R_SH_TLS_TPOFF32 +0+14
-0+4020a8  00000097 R_SH_TLS_TPOFF32 +0+00
-0+4020ac  00000097 R_SH_TLS_TPOFF32 +0+20
-0+4020b0  00000097 R_SH_TLS_TPOFF32 +0+10
-0+4130d0  00000197 R_SH_TLS_TPOFF32 +0+ +sG3 \+ 0
-0+4130d4  00000397 R_SH_TLS_TPOFF32 +0+ +sG2 \+ 0
-0+4130d8  00000497 R_SH_TLS_TPOFF32 +0+ +sG4 \+ 0
-0+4130dc  0000[0-9a-f]+97 R_SH_TLS_TPOFF32 +0+ +sG1 \+ 0
+0+4130c8  00000197 R_SH_TLS_TPOFF32 +0+ +sG3 \+ 0
+0+4130cc  00000397 R_SH_TLS_TPOFF32 +0+ +sG2 \+ 0
+0+4130d0  00000497 R_SH_TLS_TPOFF32 +0+ +sG4 \+ 0
+0+4130d4  0000[0-9a-f]+97 R_SH_TLS_TPOFF32 +0+ +sG1 \+ 0
 
 Relocation section '\.rela\.plt' at offset 0x[0-9a-f]+ contains 1 entries:
  Offset +Info +Type +Sym\.Value +Sym\. Name \+ Addend
-0+4130cc  000005a4 R_SH_JMP_SLOT +[0-9a-f]+ +__tls_get_addr \+ [0-9a-f]+
+0+4130c4  000005a4 R_SH_JMP_SLOT +[0-9a-f]+ +__tls_get_addr \+ [0-9a-f]+
 
 Symbol table '\.dynsym' contains [0-9]+ entries:
  +Num: +Value +Size Type +Bind +Vis +Ndx Name
@@ -135,7 +120,7 @@ Symbol table '\.symtab' contains [0-9]+ entries:
  +[0-9]+: 00000004 +0 TLS +GLOBAL DEFAULT +10 sg2
  +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG1
  +[0-9]+: 00000010 +0 TLS +GLOBAL HIDDEN +10 sh1
- +[0-9]+: 004130e0 +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: 004130d8 +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
  +[0-9]+: [0-9a-f]+ +0 OBJECT  GLOBAL DEFAULT  ABS _GLOBAL_OFFSET_TABLE_
  +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
  +[0-9]+: 00000014 +0 TLS +GLOBAL HIDDEN +10 sh2
diff --git a/ld/testsuite/ld-sh/tlsbin-3.d b/ld/testsuite/ld-sh/tlsbin-3.d
index 59600d4..5a3222b 100644
--- a/ld/testsuite/ld-sh/tlsbin-3.d
+++ b/ld/testsuite/ld-sh/tlsbin-3.d
@@ -8,5 +8,5 @@
 .*: +file format elf32-sh.*
 
 Contents of section \.got:
- 4130c0 [0-9a-f]+ 00000000 00000000 [0-9a-f]+  .*
- 4130d0 00000000 00000000 00000000 00000000  .*
+ 4130b8 [0-9a-f]+ 00000000 00000000 [0-9a-f]+  .*
+ 4130c8 00000000 00000000 00000000 00000000  .*
diff --git a/ld/testsuite/ld-sh/tlstpoff-1.d b/ld/testsuite/ld-sh/tlstpoff-1.d
index 2364b1e..25de25b 100644
--- a/ld/testsuite/ld-sh/tlstpoff-1.d
+++ b/ld/testsuite/ld-sh/tlstpoff-1.d
@@ -16,7 +16,7 @@ Disassembly of section \.text:
   [0-9a-f]+:	0c 3c       	add	r0,r12
   [0-9a-f]+:	02 d0       	mov.l	[0-9a-f]+ <foo\+0x14>,r0	! 0xc
   [0-9a-f]+:	12 01       	stc	gbr,r1
-  [0-9a-f]+:	ce 00       	mov.l	@\(r0,r12\),r0
+  [0-9a-f]+:	09 00       	nop	
   [0-9a-f]+:	03 a0       	bra	[0-9a-f]+ <foo\+0x18>
   [0-9a-f]+:	0c 31       	add	r0,r1
   [0-9a-f]+:	09 00       	nop	
diff --git a/ld/testsuite/ld-sh/tlstpoff-2.d b/ld/testsuite/ld-sh/tlstpoff-2.d
index ee928fd..519c6ef 100644
--- a/ld/testsuite/ld-sh/tlstpoff-2.d
+++ b/ld/testsuite/ld-sh/tlstpoff-2.d
@@ -5,8 +5,4 @@
 #readelf: -r
 #target: sh*-*-linux* sh*-*-netbsd*
 
-Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 2 entries:
- Offset +Info +Type +Sym\.Value +Sym\. Name \+ Addend
-0+[0-9a-f]+  00000097 R_SH_TLS_TPOFF32 +0+04
-0+[0-9a-f]+  00000097 R_SH_TLS_TPOFF32 +0+04
-
+There are no relocations in this file.