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| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-11-03 14:21:32 +0000 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-11-03 14:29:31 +0000 |
| commit | fd65497db4098140490e59e3dbf4709da5536081 (patch) | |
| tree | 2f730ad7d7e19dee1420de5a7641dfd59cb717a4 /include | |
| parent | b0d0d02bde06c61969160c0c5a3d7f48daa8b24a (diff) | |
| download | gdb-fd65497db4098140490e59e3dbf4709da5536081.zip gdb-fd65497db4098140490e59e3dbf4709da5536081.tar.gz gdb-fd65497db4098140490e59e3dbf4709da5536081.tar.bz2 | |
[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7
Armv8.7 architecture introduces the "accelerator extension", aka
load/store of 64 bytes. New atomic load/store instructions are: LD64B,
ST64B, ST64BV and ST64BV0.
This patch adds:
+ New feature +ls64 to -march command line.
+ New atomic load/store instructions associated with above feature.
For more details regarding atomic 64-byte load/store instruction for
Armv8.7 please refer to Arm A64 Instruction set documentation for
Armv8-A architecture profile, see document page 157 for load
instruction, and pages 414-418 for store instructions of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 5 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 4 |
2 files changed, 8 insertions, 1 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index d11f36f..b403c5c 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2020-11-03 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * opcode/aarch64.h (AARCH64_FEATURE_LS64): New +ls64 feature flag. + (AARCH64_ARCH_V8_7): Add LS64 as part of Armv8.7-a. + 2020-10-30 H.J. Lu <hongjiu.lu@intel.com> PR gas/26703 diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 7d484ad..07eb911 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -52,6 +52,7 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */ #define AARCH64_FEATURE_V8_7 (1ULL << 13) /* Armv8.7 processors. */ #define AARCH64_FEATURE_CSRE (1ULL << 14) /* CSRE feature. */ +#define AARCH64_FEATURE_LS64 (1ULL << 15) /* Atomic 64-byte load/store. */ #define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */ #define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */ #define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */ @@ -131,7 +132,8 @@ typedef uint32_t aarch64_insn; | AARCH64_FEATURE_BFLOAT16 \ | AARCH64_FEATURE_I8MM) #define AARCH64_ARCH_V8_7 AARCH64_FEATURE (AARCH64_ARCH_V8_6, \ - AARCH64_FEATURE_V8_7) + AARCH64_FEATURE_V8_7 \ + | AARCH64_FEATURE_LS64) #define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \ AARCH64_FEATURE_V8_R) \ & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR)) |