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authorRichard Sandiford <rdsandiford@googlemail.com>2011-07-24 14:20:15 +0000
committerRichard Sandiford <rdsandiford@googlemail.com>2011-07-24 14:20:15 +0000
commitdf58fc944dbc6d5efd8d3826241b64b6af22f447 (patch)
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2011-02-25 Chao-ying Fu <fu@mips.com> Ilie Garbacea <ilie@mips.com> Maciej W. Rozycki <macro@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Catherine Moore <clm@codesourcery.com> Richard Sandiford <rdsandiford@googlemail.com> * archures.c (bfd_mach_mips_micromips): New macro. * cpu-mips.c (I_micromips): New enum value. (arch_info_struct): Add bfd_mach_mips_micromips. * elfxx-mips.h (_bfd_mips_elf_is_target_special_symbol): New prototype. (_bfd_mips_elf_relax_section): Likewise. (_bfd_mips16_elf_reloc_unshuffle): Rename to... (_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS ASE. (_bfd_mips16_elf_reloc_shuffle): Rename to... (_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE. (gprel16_reloc_p): Handle microMIPS ASE. (literal_reloc_p): New function. * elf32-mips.c (elf_micromips_howto_table_rel): New variable. (_bfd_mips_elf32_gprel16_reloc): Handle microMIPS ASE. (mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle and _bfd_mips_elf_reloc_shuffle changes. (mips_elf_gprel32_reloc): Update comment. (micromips_reloc_map): New variable. (bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE. (mips_elf32_rtype_to_howto): Likewise. (mips_info_to_howto_rel): Likewise. (bfd_elf32_bfd_is_target_special_symbol): Define. (bfd_elf32_bfd_relax_section): Likewise. * elf64-mips.c (micromips_elf64_howto_table_rel): New variable. (micromips_elf64_howto_table_rela): Likewise. (mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle and _bfd_mips_elf_reloc_shuffle changes. (micromips_reloc_map): Likewise. (bfd_elf64_bfd_reloc_type_lookup): Handle microMIPS ASE. (bfd_elf64_bfd_reloc_name_lookup): Likewise. (mips_elf64_rtype_to_howto): Likewise. (bfd_elf64_bfd_is_target_special_symbol): Define. * elfn32-mips.c (elf_micromips_howto_table_rel): New variable. (elf_micromips_howto_table_rela): Likewise. (mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle and _bfd_mips_elf_reloc_shuffle changes. (micromips_reloc_map): Likewise. (bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE. (bfd_elf32_bfd_reloc_name_lookup): Likewise. (mips_elf_n32_rtype_to_howto): Likewise. (bfd_elf32_bfd_is_target_special_symbol): Define. * elfxx-mips.c (LA25_LUI_MICROMIPS_1): New macro. (LA25_LUI_MICROMIPS_2): Likewise. (LA25_J_MICROMIPS_1, LA25_J_MICROMIPS_2): Likewise. (LA25_ADDIU_MICROMIPS_1, LA25_ADDIU_MICROMIPS_2): Likewise. (TLS_RELOC_P): Handle microMIPS ASE. (mips_elf_create_stub_symbol): Adjust value of stub symbol if target is a microMIPS function. (micromips_reloc_p): New function. (micromips_reloc_shuffle_p): Likewise. (got16_reloc_p, call16_reloc_p): Handle microMIPS ASE. (got_disp_reloc_p, got_page_reloc_p): New functions. (got_ofst_reloc_p): Likewise. (got_hi16_reloc_p, got_lo16_reloc_p): Likewise. (call_hi16_reloc_p, call_lo16_reloc_p): Likewise. (hi16_reloc_p, lo16_reloc_p, jal_reloc_p): Handle microMIPS ASE. (micromips_branch_reloc_p): New function. (tls_gd_reloc_p, tls_ldm_reloc_p): Likewise. (tls_gottprel_reloc_p): Likewise. (_bfd_mips16_elf_reloc_unshuffle): Rename to... (_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS ASE. (_bfd_mips16_elf_reloc_shuffle): Rename to... (_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE. (_bfd_mips_elf_lo16_reloc): Handle microMIPS ASE. (mips_tls_got_index, mips_elf_got_page): Likewise. (mips_elf_create_local_got_entry): Likewise. (mips_elf_relocation_needs_la25_stub): Likewise. (mips_elf_calculate_relocation): Likewise. (mips_elf_perform_relocation): Likewise. (_bfd_mips_elf_symbol_processing): Likewise. (_bfd_mips_elf_add_symbol_hook): Likewise. (_bfd_mips_elf_link_output_symbol_hook): Likewise. (mips_elf_add_lo16_rel_addend): Likewise. (_bfd_mips_elf_check_relocs): Likewise. (mips_elf_adjust_addend): Likewise. (_bfd_mips_elf_relocate_section): Likewise. (mips_elf_create_la25_stub): Likewise. (_bfd_mips_vxworks_finish_dynamic_symbol): Likewise. (_bfd_mips_elf_gc_sweep_hook): Likewise. (_bfd_mips_elf_is_target_special_symbol): New function. (mips_elf_relax_delete_bytes): Likewise. (opcode_descriptor): New structure. (RA): New macro. (OP32_SREG, OP32_TREG, OP16_VALID_REG): Likewise. (b_insns_32, bc_insn_32, bz_insn_32, bzal_insn_32): New variables. (beq_insn_32): Likewise. (b_insn_16, bz_insn_16): New variables. (BZC32_REG_FIELD): New macro. (bz_rs_insns_32, bz_rt_insns_32): New variables. (bzc_insns_32, bz_insns_16):Likewise. (BZ16_REG, BZ16_REG_FIELD): New macros. (jal_insn_32_bd16, jal_insn_32_bd32): New variables. (jal_x_insn_32_bd32): Likewise. (j_insn_32, jalr_insn_32): Likewise. (ds_insns_32_bd16, ds_insns_32_bd32): Likewise. (jalr_insn_16_bd16, jalr_insn_16_bd32, jr_insn_16): Likewise. (JR16_REG): New macro. (ds_insns_16_bd16): New variable. (lui_insn): Likewise. (addiu_insn, addiupc_insn): Likewise. (ADDIUPC_REG_FIELD): New macro. (MOVE32_RD, MOVE32_RS): Likewise. (MOVE16_RD_FIELD, MOVE16_RS_FIELD): Likewise. (move_insns_32, move_insns_16): New variables. (nop_insn_32, nop_insn_16): Likewise. (MATCH): New macro. (find_match): New function. (check_br16_dslot, check_br32_dslot): Likewise. (check_br16, check_br32): Likewise. (IS_BITSIZE): New macro. (check_4byte_branch): New function. (_bfd_mips_elf_relax_section): Likewise. (_bfd_mips_elf_merge_private_bfd_data): Disallow linking MIPS16 and microMIPS modules together. (_bfd_mips_elf_print_private_bfd_data): Handle microMIPS ASE. * reloc.c (BFD_RELOC_MICROMIPS_7_PCREL_S1): New relocation. (BFD_RELOC_MICROMIPS_10_PCREL_S1): Likewise. (BFD_RELOC_MICROMIPS_16_PCREL_S1): Likewise. (BFD_RELOC_MICROMIPS_GPREL16): Likewise. (BFD_RELOC_MICROMIPS_JMP, BFD_RELOC_MICROMIPS_HI16): Likewise. (BFD_RELOC_MICROMIPS_HI16_S): Likewise. (BFD_RELOC_MICROMIPS_LO16): Likewise. (BFD_RELOC_MICROMIPS_LITERAL): Likewise. (BFD_RELOC_MICROMIPS_GOT16): Likewise. (BFD_RELOC_MICROMIPS_CALL16): Likewise. (BFD_RELOC_MICROMIPS_GOT_HI16): Likewise. (BFD_RELOC_MICROMIPS_GOT_LO16): Likewise. (BFD_RELOC_MICROMIPS_CALL_HI16): Likewise. (BFD_RELOC_MICROMIPS_CALL_LO16): Likewise. (BFD_RELOC_MICROMIPS_SUB): Likewise. (BFD_RELOC_MICROMIPS_GOT_PAGE): Likewise. (BFD_RELOC_MICROMIPS_GOT_OFST): Likewise. (BFD_RELOC_MICROMIPS_GOT_DISP): Likewise. (BFD_RELOC_MICROMIPS_HIGHEST): Likewise. (BFD_RELOC_MICROMIPS_HIGHER): Likewise. (BFD_RELOC_MICROMIPS_SCN_DISP): Likewise. (BFD_RELOC_MICROMIPS_JALR): Likewise. (BFD_RELOC_MICROMIPS_TLS_GD): Likewise. (BFD_RELOC_MICROMIPS_TLS_LDM): Likewise. (BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16): Likewise. (BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16): Likewise. (BFD_RELOC_MICROMIPS_TLS_GOTTPREL): Likewise. (BFD_RELOC_MICROMIPS_TLS_TPREL_HI16): Likewise. (BFD_RELOC_MICROMIPS_TLS_TPREL_LO16): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. binutils/ 2011-02-25 Chao-ying Fu <fu@mips.com> Maciej W. Rozycki <macro@codesourcery.com> * readelf.c (get_machine_flags): Handle microMIPS ASE. (get_mips_symbol_other): Likewise. gas/ 2011-02-25 Maciej W. Rozycki <macro@codesourcery.com> Chao-ying Fu <fu@mips.com> Richard Sandiford <rdsandiford@googlemail.com> * config/tc-mips.h (mips_segment_info): Add one bit for microMIPS. (TC_LABEL_IS_LOCAL): New macro. (mips_label_is_local): New prototype. * config/tc-mips.c (S0, S7): New macros. (emit_branch_likely_macro): New variable. (mips_set_options): Add micromips. (mips_opts): Initialise micromips to -1. (file_ase_micromips): New variable. (CPU_HAS_MICROMIPS): New macro. (hilo_interlocks): Set for microMIPS too. (gpr_interlocks): Likewise. (cop_interlocks): Likewise. (cop_mem_interlocks): Likewise. (HAVE_CODE_COMPRESSION): New macro. (micromips_op_hash): New variable. (micromips_nop16_insn, micromips_nop32_insn): New variables. (NOP_INSN): Handle microMIPS ASE. (mips32_to_micromips_reg_b_map): New macro. (mips32_to_micromips_reg_c_map): Likewise. (mips32_to_micromips_reg_d_map): Likewise. (mips32_to_micromips_reg_e_map): Likewise. (mips32_to_micromips_reg_f_map): Likewise. (mips32_to_micromips_reg_g_map): Likewise. (mips32_to_micromips_reg_l_map): Likewise. (mips32_to_micromips_reg_n_map): Likewise. (mips32_to_micromips_reg_h_map): New variable. (mips32_to_micromips_reg_m_map): Likewise. (mips32_to_micromips_reg_q_map): Likewise. (micromips_to_32_reg_h_map): New variable. (micromips_to_32_reg_i_map): Likewise. (micromips_to_32_reg_m_map): Likewise. (micromips_to_32_reg_q_map): Likewise. (micromips_to_32_reg_b_map): New macro. (micromips_to_32_reg_c_map): Likewise. (micromips_to_32_reg_d_map): Likewise. (micromips_to_32_reg_e_map): Likewise. (micromips_to_32_reg_f_map): Likewise. (micromips_to_32_reg_g_map): Likewise. (micromips_to_32_reg_l_map): Likewise. (micromips_to_32_reg_n_map): Likewise. (micromips_imm_b_map, micromips_imm_c_map): New macros. (RELAX_DELAY_SLOT_16BIT): New macro. (RELAX_DELAY_SLOT_SIZE_FIRST): Likewise. (RELAX_DELAY_SLOT_SIZE_SECOND): Likewise. (RELAX_MICROMIPS_ENCODE, RELAX_MICROMIPS_P): New macros. (RELAX_MICROMIPS_TYPE, RELAX_MICROMIPS_AT): Likewise. (RELAX_MICROMIPS_U16BIT, RELAX_MICROMIPS_UNCOND): Likewise. (RELAX_MICROMIPS_COMPACT, RELAX_MICROMIPS_LINK): Likewise. (RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16): Likewise. (RELAX_MICROMIPS_MARK_TOOFAR16): Likewise. (RELAX_MICROMIPS_CLEAR_TOOFAR16): Likewise. (RELAX_MICROMIPS_TOOFAR32): Likewise. (RELAX_MICROMIPS_MARK_TOOFAR32): Likewise. (RELAX_MICROMIPS_CLEAR_TOOFAR32): Likewise. (INSERT_OPERAND, EXTRACT_OPERAND): Handle microMIPS ASE. (mips_macro_warning): Add delay_slot_16bit_p, delay_slot_32bit_p, fsize and insns. (mips_mark_labels): New function. (mips16_small, mips16_ext): Remove variables, replacing with... (forced_insn_size): ... this. (append_insn, mips16_ip): Update accordingly. (micromips_insn_length): New function. (insn_length): Return the length of microMIPS instructions. (mips_record_mips16_mode): Rename to... (mips_record_compressed_mode): ... this. Handle microMIPS ASE. (install_insn): Handle microMIPS ASE. (reglist_lookup): New function. (is_size_valid, is_delay_slot_valid): Likewise. (md_begin): Handle microMIPS ASE. (md_assemble): Likewise. Update for append_insn interface change. (micromips_reloc_p): New function. (got16_reloc_p): Handle microMIPS ASE. (hi16_reloc_p): Likewise. (lo16_reloc_p): Likewise. (jmp_reloc_p): New function. (jalr_reloc_p): Likewise. (matching_lo_reloc): Handle microMIPS ASE. (insn_uses_reg, reg_needs_delay): Likewise. (mips_move_labels): Likewise. (mips16_mark_labels): Rename to... (mips_compressed_mark_labels): ... this. Handle microMIPS ASE. (gpr_mod_mask): New function. (gpr_read_mask, gpr_write_mask): Handle microMIPS ASE. (fpr_read_mask, fpr_write_mask): Likewise. (insns_between, nops_for_vr4130, nops_for_insn): Likewise. (fix_loongson2f_nop, fix_loongson2f_jump): Likewise. (MICROMIPS_LABEL_CHAR): New macro. (micromips_target_label, micromips_target_name): New variables. (micromips_label_name, micromips_label_expr): New functions. (micromips_label_inc, micromips_add_label): Likewise. (mips_label_is_local): Likewise. (micromips_map_reloc): Likewise. (can_swap_branch_p): Handle microMIPS ASE. (append_insn): Add expansionp argument. Handle microMIPS ASE. (start_noreorder, end_noreorder): Handle microMIPS ASE. (macro_start, macro_warning, macro_end): Likewise. (brk_fmt, cop12_fmt, jalr_fmt, lui_fmt): New variables. (mem12_fmt, mfhl_fmt, shft_fmt, trap_fmt): Likewise. (BRK_FMT, COP12_FMT, JALR_FMT, LUI_FMT): New macros. (MEM12_FMT, MFHL_FMT, SHFT_FMT, TRAP_FMT): Likewise. (macro_build): Handle microMIPS ASE. Update for append_insn interface change. (mips16_macro_build): Update for append_insn interface change. (macro_build_jalr): Handle microMIPS ASE. (macro_build_lui): Likewise. Simplify. (load_register): Handle microMIPS ASE. (load_address): Likewise. (move_register): Likewise. (macro_build_branch_likely): New function. (macro_build_branch_ccl): Likewise. (macro_build_branch_rs): Likewise. (macro_build_branch_rsrt): Likewise. (macro): Handle microMIPS ASE. (validate_micromips_insn): New function. (expr_const_in_range): Likewise. (mips_ip): Handle microMIPS ASE. (options): Add OPTION_MICROMIPS and OPTION_NO_MICROMIPS. (md_longopts): Add mmicromips and mno-micromips. (md_parse_option): Handle OPTION_MICROMIPS and OPTION_NO_MICROMIPS. (mips_after_parse_args): Handle microMIPS ASE. (md_pcrel_from): Handle microMIPS relocations. (mips_force_relocation): Likewise. (md_apply_fix): Likewise. (mips_align): Handle microMIPS ASE. (s_mipsset): Likewise. (s_cpload, s_cpsetup, s_cpreturn): Use relocation wrappers. (s_dtprel_internal): Likewise. (s_gpword, s_gpdword): Likewise. (s_insn): Handle microMIPS ASE. (s_mips_stab): Likewise. (relaxed_micromips_32bit_branch_length): New function. (relaxed_micromips_16bit_branch_length): New function. (md_estimate_size_before_relax): Handle microMIPS ASE. (mips_fix_adjustable): Likewise. (tc_gen_reloc): Handle microMIPS relocations. (mips_relax_frag): Handle microMIPS ASE. (md_convert_frag): Likewise. (mips_frob_file_after_relocs): Likewise. (mips_elf_final_processing): Likewise. (mips_nop_opcode): Likewise. (mips_handle_align): Likewise. (md_show_usage): Handle microMIPS options. * symbols.c (TC_LABEL_IS_LOCAL): New macro. (S_IS_LOCAL): Add a TC_LABEL_IS_LOCAL check. * doc/as.texinfo (Target MIPS options): Add -mmicromips and -mno-micromips. (-mmicromips, -mno-micromips): New options. * doc/c-mips.texi (-mmicromips, -mno-micromips): New options. (MIPS ISA): Document .set micromips and .set nomicromips. (MIPS insn): Update for microMIPS support. gas/testsuite/ 2011-02-25 Maciej W. Rozycki <macro@codesourcery.com> Chao-ying Fu <fu@mips.com> Richard Sandiford <rdsandiford@googlemail.com> * gas/mips/micromips.d: New test. * gas/mips/micromips-branch-delay.d: Likewise. * gas/mips/micromips-branch-relax.d: Likewise. * gas/mips/micromips-branch-relax-pic.d: Likewise. * gas/mips/micromips-size-1.d: Likewise. * gas/mips/micromips-trap.d: Likewise. * gas/mips/micromips.l: New stderr output. * gas/mips/micromips-branch-delay.l: Likewise. * gas/mips/micromips-branch-relax.l: Likewise. * gas/mips/micromips-branch-relax-pic.l: Likewise. * gas/mips/micromips-size-0.l: New list test. * gas/mips/micromips-size-1.l: New stderr output. * gas/mips/micromips.s: New test source. * gas/mips/micromips-branch-delay.s: Likewise. * gas/mips/micromips-branch-relax.s: Likewise. * gas/mips/micromips-size-0.s: Likewise. * gas/mips/micromips-size-1.s: Likewise. * gas/mips/mips.exp: Run the new tests. * gas/mips/dli.s: Use .p2align. * gas/mips/elf_ase_micromips.d: New test. * gas/mips/elf_ase_micromips-2.d: Likewise. * gas/mips/micromips@abs.d: Likewise. * gas/mips/micromips@add.d: Likewise. * gas/mips/micromips@alnv_ps-swap.d: Likewise. * gas/mips/micromips@and.d: Likewise. * gas/mips/micromips@beq.d: Likewise. * gas/mips/micromips@bge.d: Likewise. * gas/mips/micromips@bgeu.d: Likewise. * gas/mips/micromips@blt.d: Likewise. * gas/mips/micromips@bltu.d: Likewise. * gas/mips/micromips@branch-likely.d: Likewise. * gas/mips/micromips@branch-misc-1.d: Likewise. * gas/mips/micromips@branch-misc-2-64.d: Likewise. * gas/mips/micromips@branch-misc-2.d: Likewise. * gas/mips/micromips@branch-misc-2pic-64.d: Likewise. * gas/mips/micromips@branch-misc-2pic.d: Likewise. * gas/mips/micromips@branch-misc-4-64.d: Likewise. * gas/mips/micromips@branch-misc-4.d: Likewise. * gas/mips/micromips@branch-self.d: Likewise. * gas/mips/micromips@cache.d: Likewise. * gas/mips/micromips@daddi.d: Likewise. * gas/mips/micromips@dli.d: Likewise. * gas/mips/micromips@elf-jal.d: Likewise. * gas/mips/micromips@elf-rel2.d: Likewise. * gas/mips/micromips@elfel-rel2.d: Likewise. * gas/mips/micromips@elf-rel4.d: Likewise. * gas/mips/micromips@jal-svr4pic.d: Likewise. * gas/mips/micromips@jal-svr4pic-noreorder.d: Likewise. * gas/mips/micromips@lb-svr4pic-ilocks.d: Likewise. * gas/mips/micromips@li.d: Likewise. * gas/mips/micromips@loc-swap-dis.d: Likewise. * gas/mips/micromips@loc-swap.d: Likewise. * gas/mips/micromips@mips1-fp.d: Likewise. * gas/mips/micromips@mips32-cp2.d: Likewise. * gas/mips/micromips@mips32-imm.d: Likewise. * gas/mips/micromips@mips32-sf32.d: Likewise. * gas/mips/micromips@mips32.d: Likewise. * gas/mips/micromips@mips32r2-cp2.d: Likewise. * gas/mips/micromips@mips32r2-fp32.d: Likewise. * gas/mips/micromips@mips32r2-sync.d: Likewise. * gas/mips/micromips@mips32r2.d: Likewise. * gas/mips/micromips@mips4-branch-likely.d: Likewise. * gas/mips/micromips@mips4-fp.d: Likewise. * gas/mips/micromips@mips4.d: Likewise. * gas/mips/micromips@mips5.d: Likewise. * gas/mips/micromips@mips64-cp2.d: Likewise. * gas/mips/micromips@mips64.d: Likewise. * gas/mips/micromips@mips64r2.d: Likewise. * gas/mips/micromips@pref.d: Likewise. * gas/mips/micromips@relax-at.d: Likewise. * gas/mips/micromips@relax.d: Likewise. * gas/mips/micromips@rol-hw.d: Likewise. * gas/mips/micromips@uld2-eb.d: Likewise. * gas/mips/micromips@uld2-el.d: Likewise. * gas/mips/micromips@ulh2-eb.d: Likewise. * gas/mips/micromips@ulh2-el.d: Likewise. * gas/mips/micromips@ulw2-eb-ilocks.d: Likewise. * gas/mips/micromips@ulw2-el-ilocks.d: Likewise. * gas/mips/cache.d: Likewise. * gas/mips/daddi.d: Likewise. * gas/mips/mips32-imm.d: Likewise. * gas/mips/pref.d: Likewise. * gas/mips/elf-rel27.d: Handle microMIPS ASE. * gas/mips/l_d.d: Likewise. * gas/mips/l_d-n32.d: Likewise. * gas/mips/l_d-n64.d: Likewise. * gas/mips/ld.d: Likewise. * gas/mips/ld-n32.d: Likewise. * gas/mips/ld-n64.d: Likewise. * gas/mips/s_d.d: Likewise. * gas/mips/s_d-n32.d: Likewise. * gas/mips/s_d-n64.d: Likewise. * gas/mips/sd.d: Likewise. * gas/mips/sd-n32.d: Likewise. * gas/mips/sd-n64.d: Likewise. * gas/mips/mips32.d: Update immediates. * gas/mips/micromips@mips32-cp2.s: New test source. * gas/mips/micromips@mips32-imm.s: Likewise. * gas/mips/micromips@mips32r2-cp2.s: Likewise. * gas/mips/micromips@mips64-cp2.s: Likewise. * gas/mips/cache.s: Likewise. * gas/mips/daddi.s: Likewise. * gas/mips/mips32-imm.s: Likewise. * gas/mips/elf-rel4.s: Handle microMIPS ASE. * gas/mips/lb-pic.s: Likewise. * gas/mips/ld.s: Likewise. * gas/mips/mips32.s: Likewise. * gas/mips/mips.exp: Add the micromips arch. Exclude mips16e from micromips. Run mips32-imm. * gas/mips/jal-mask-11.d: New test. * gas/mips/jal-mask-12.d: Likewise. * gas/mips/micromips@jal-mask-11.d: Likewise. * gas/mips/jal-mask-1.s: Source for the new tests. * gas/mips/jal-mask-21.d: New test. * gas/mips/jal-mask-22.d: Likewise. * gas/mips/micromips@jal-mask-12.d: Likewise. * gas/mips/jal-mask-2.s: Source for the new tests. * gas/mips/mips.exp: Run the new tests. * gas/mips/mips16-e.d: Add --special-syms to `objdump'. * gas/mips/tmips16-e.d: Likewise. * gas/mips/mipsel16-e.d: Likewise. * gas/mips/tmipsel16-e.d: Likewise. * gas/mips/and.s: Adjust padding. * gas/mips/beq.s: Likewise. * gas/mips/bge.s: Likewise. * gas/mips/bgeu.s: Likewise. * gas/mips/blt.s: Likewise. * gas/mips/bltu.s: Likewise. * gas/mips/branch-misc-2.s: Likewise. * gas/mips/jal.s: Likewise. * gas/mips/li.s: Likewise. * gas/mips/mips4.s: Likewise. * gas/mips/mips4-fp.s: Likewise. * gas/mips/relax.s: Likewise. * gas/mips/and.d: Update accordingly. * gas/mips/elf-jal.d: Likewise. * gas/mips/jal.d: Likewise. * gas/mips/li.d: Likewise. * gas/mips/relax-at.d: Likewise. * gas/mips/relax.d: Likewise. include/elf/ 2011-02-25 Chao-ying Fu <fu@mips.com> Maciej W. Rozycki <macro@codesourcery.com> * mips.h (R_MICROMIPS_min): New relocations. (R_MICROMIPS_26_S1): Likewise. (R_MICROMIPS_HI16, R_MICROMIPS_LO16): Likewise. (R_MICROMIPS_GPREL16, R_MICROMIPS_LITERAL): Likewise. (R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1): Likewise. (R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1): Likewise. (R_MICROMIPS_CALL16, R_MICROMIPS_GOT_DISP): Likewise. (R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST): Likewise. (R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16): Likewise. (R_MICROMIPS_SUB, R_MICROMIPS_HIGHER): Likewise. (R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16): Likewise. (R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP): Likewise. (R_MICROMIPS_JALR, R_MICROMIPS_HI0_LO16): Likewise. (R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM): Likewise. (R_MICROMIPS_TLS_DTPREL_HI, R_MICROMIPS_TLS_DTPREL_LO): Likewise. (R_MICROMIPS_TLS_GOTTPREL): Likewise. (R_MICROMIPS_TLS_TPREL_HI16): Likewise. (R_MICROMIPS_TLS_TPREL_LO16): Likewise. (R_MICROMIPS_GPREL7_S2, R_MICROMIPS_PC23_S2): Likewise. (R_MICROMIPS_max): Likewise. (EF_MIPS_ARCH_ASE_MICROMIPS): New macro. (STO_MIPS_ISA, STO_MIPS_FLAGS): Likewise. (ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT): Likewise. (STO_MICROMIPS): Likewise. (ELF_ST_IS_MICROMIPS, ELF_ST_SET_MICROMIPS): Likewise. (ELF_ST_IS_COMPRESSED): Likewise. (STO_MIPS_PLT, STO_MIPS_PIC): Rework. (ELF_ST_IS_MIPS_PIC, ELF_ST_SET_MIPS_PIC): Likewise. (STO_MIPS16, ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): Likewise. include/opcode/ 2011-02-25 Chao-ying Fu <fu@mips.com> Maciej W. Rozycki <macro@codesourcery.com> * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros. (OP_MASK_STYPE, OP_SH_STYPE): Likewise. (OP_MASK_CODE10, OP_SH_CODE10): Likewise. (OP_MASK_TRAP, OP_SH_TRAP): Likewise. (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise. (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise. (OP_MASK_RS3, OP_SH_RS3): Likewise. (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise. (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise. (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise. (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise. (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise. (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise. (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise. (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise. (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise. (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise. (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise. (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise. (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise. (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise. (INSN_WRITE_GPR_S): New macro. (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise. (INSN2_READ_FPR_D): Likewise. (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise. (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise. (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise. (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise. (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise. (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise. (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise. (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise. (CPU_MICROMIPS): New macro. (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values. (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise. (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise. (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise. (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise. (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise. (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise. (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise. (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise. (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise. (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise. (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise. (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise. (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros. (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise. (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise. (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise. (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise. (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise. (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise. (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise. (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise. (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise. (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise. (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise. (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise. (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise. (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise. (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise. (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise. (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise. (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise. (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise. (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise. (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise. (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise. (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise. (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise. (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise. (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise. (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise. (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise. (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise. (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise. (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise. (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise. (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise. (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise. (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise. (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise. (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise. (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise. (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise. (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise. (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise. (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise. (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise. (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise. (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise. (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise. (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise. (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise. (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise. (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise. (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise. (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise. (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise. (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise. (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise. (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise. (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise. (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise. (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise. (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise. (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise. (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise. (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise. (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise. (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise. (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise. (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise. (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise. (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise. (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise. (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise. (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise. (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise. (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise. (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise. (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise. (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise. (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise. (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise. (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise. (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise. (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise. (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise. (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise. (micromips_opcodes): New declaration. (bfd_micromips_num_opcodes): Likewise. ld/testsuite/ 2011-02-25 Catherine Moore <clm@codesourcery.com> Chao-ying Fu <fu@mips.com> Maciej W. Rozycki <macro@codesourcery.com> * lib/ld-lib.exp (run_dump_test): Support distinct assembler flags for the same source named multiple times. * ld-mips-elf/jalx-1.s: New test source. * ld-mips-elf/jalx-1.d: New test output. * ld-mips-elf/jalx-1.ld: New test linker script. * ld-mips-elf/jalx-2-main.s: New test source. * ld-mips-elf/jalx-2-ex.s: Likewise. * ld-mips-elf/jalx-2-printf.s: Likewise. * ld-mips-elf/jalx-2.dd: New test output. * ld-mips-elf/jalx-2.ld: New test linker script. * ld-mips-elf/mips16-and-micromips.d: New test. * ld-mips-elf/mips-elf.exp: Run the new tests opcodes/ 2011-02-25 Chao-ying Fu <fu@mips.com> Maciej W. Rozycki <macro@codesourcery.com> * micromips-opc.c: New file. * mips-dis.c (micromips_to_32_reg_b_map): New array. (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise. (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise. (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise. (micromips_to_32_reg_q_map): Likewise. (micromips_imm_b_map, micromips_imm_c_map): Likewise. (micromips_ase): New variable. (is_micromips): New function. (set_default_mips_dis_options): Handle microMIPS ASE. (print_insn_micromips): New function. (is_compressed_mode_p): Likewise. (_print_insn_mips): Handle microMIPS instructions. * Makefile.am (CFILES): Add micromips-opc.c. * configure.in (bfd_mips_arch): Add micromips-opc.lo. * Makefile.in: Regenerate. * configure: Regenerate. * mips-dis.c (micromips_to_32_reg_h_map): New variable. (micromips_to_32_reg_i_map): Likewise. (micromips_to_32_reg_m_map): Likewise. (micromips_to_32_reg_n_map): New macro.
Diffstat (limited to 'include')
-rw-r--r--include/elf/ChangeLog33
-rw-r--r--include/elf/mips.h84
-rw-r--r--include/opcode/ChangeLog144
-rw-r--r--include/opcode/mips.h557
4 files changed, 810 insertions, 8 deletions
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 3111448..39152ac 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,36 @@
+2011-07-24 Chao-ying Fu <fu@mips.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h (R_MICROMIPS_min): New relocations.
+ (R_MICROMIPS_26_S1): Likewise.
+ (R_MICROMIPS_HI16, R_MICROMIPS_LO16): Likewise.
+ (R_MICROMIPS_GPREL16, R_MICROMIPS_LITERAL): Likewise.
+ (R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1): Likewise.
+ (R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1): Likewise.
+ (R_MICROMIPS_CALL16, R_MICROMIPS_GOT_DISP): Likewise.
+ (R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST): Likewise.
+ (R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16): Likewise.
+ (R_MICROMIPS_SUB, R_MICROMIPS_HIGHER): Likewise.
+ (R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16): Likewise.
+ (R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP): Likewise.
+ (R_MICROMIPS_JALR, R_MICROMIPS_HI0_LO16): Likewise.
+ (R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM): Likewise.
+ (R_MICROMIPS_TLS_DTPREL_HI, R_MICROMIPS_TLS_DTPREL_LO): Likewise.
+ (R_MICROMIPS_TLS_GOTTPREL): Likewise.
+ (R_MICROMIPS_TLS_TPREL_HI16): Likewise.
+ (R_MICROMIPS_TLS_TPREL_LO16): Likewise.
+ (R_MICROMIPS_GPREL7_S2, R_MICROMIPS_PC23_S2): Likewise.
+ (R_MICROMIPS_max): Likewise.
+ (EF_MIPS_ARCH_ASE_MICROMIPS): New macro.
+ (STO_MIPS_ISA, STO_MIPS_FLAGS): Likewise.
+ (ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT): Likewise.
+ (STO_MICROMIPS): Likewise.
+ (ELF_ST_IS_MICROMIPS, ELF_ST_SET_MICROMIPS): Likewise.
+ (ELF_ST_IS_COMPRESSED): Likewise.
+ (STO_MIPS_PLT, STO_MIPS_PIC): Rework.
+ (ELF_ST_IS_MIPS_PIC, ELF_ST_SET_MIPS_PIC): Likewise.
+ (STO_MIPS16, ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): Likewise.
+
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* common.h (EM_K1OM): New.
diff --git a/include/elf/mips.h b/include/elf/mips.h
index c60e8fe..db5fa54 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -102,6 +102,48 @@ START_RELOC_NUMBERS (elf_mips_reloc_type)
/* These relocations are specific to VxWorks. */
RELOC_NUMBER (R_MIPS_COPY, 126)
RELOC_NUMBER (R_MIPS_JUMP_SLOT, 127)
+
+ /* These relocations are specific to microMIPS. */
+ FAKE_RELOC (R_MICROMIPS_min, 130)
+ RELOC_NUMBER (R_MICROMIPS_26_S1, 133)
+ RELOC_NUMBER (R_MICROMIPS_HI16, 134)
+ RELOC_NUMBER (R_MICROMIPS_LO16, 135)
+ RELOC_NUMBER (R_MICROMIPS_GPREL16, 136) /* In Elf 64:
+ alias R_MICROMIPS_GPREL */
+ RELOC_NUMBER (R_MICROMIPS_LITERAL, 137)
+ RELOC_NUMBER (R_MICROMIPS_GOT16, 138) /* In Elf 64:
+ alias R_MICROMIPS_GOT */
+ RELOC_NUMBER (R_MICROMIPS_PC7_S1, 139)
+ RELOC_NUMBER (R_MICROMIPS_PC10_S1, 140)
+ RELOC_NUMBER (R_MICROMIPS_PC16_S1, 141)
+ RELOC_NUMBER (R_MICROMIPS_CALL16, 142) /* In Elf 64:
+ alias R_MICROMIPS_CALL */
+ RELOC_NUMBER (R_MICROMIPS_GOT_DISP, 145)
+ RELOC_NUMBER (R_MICROMIPS_GOT_PAGE, 146)
+ RELOC_NUMBER (R_MICROMIPS_GOT_OFST, 147)
+ RELOC_NUMBER (R_MICROMIPS_GOT_HI16, 148)
+ RELOC_NUMBER (R_MICROMIPS_GOT_LO16, 149)
+ RELOC_NUMBER (R_MICROMIPS_SUB, 150)
+ RELOC_NUMBER (R_MICROMIPS_HIGHER, 151)
+ RELOC_NUMBER (R_MICROMIPS_HIGHEST, 152)
+ RELOC_NUMBER (R_MICROMIPS_CALL_HI16, 153)
+ RELOC_NUMBER (R_MICROMIPS_CALL_LO16, 154)
+ RELOC_NUMBER (R_MICROMIPS_SCN_DISP, 155)
+ RELOC_NUMBER (R_MICROMIPS_JALR, 156)
+ RELOC_NUMBER (R_MICROMIPS_HI0_LO16, 157)
+ /* TLS relocations. */
+ RELOC_NUMBER (R_MICROMIPS_TLS_GD, 162)
+ RELOC_NUMBER (R_MICROMIPS_TLS_LDM, 163)
+ RELOC_NUMBER (R_MICROMIPS_TLS_DTPREL_HI16, 164)
+ RELOC_NUMBER (R_MICROMIPS_TLS_DTPREL_LO16, 165)
+ RELOC_NUMBER (R_MICROMIPS_TLS_GOTTPREL, 166)
+ RELOC_NUMBER (R_MICROMIPS_TLS_TPREL_HI16, 169)
+ RELOC_NUMBER (R_MICROMIPS_TLS_TPREL_LO16, 170)
+ /* microMIPS GP- and PC-relative relocations. */
+ RELOC_NUMBER (R_MICROMIPS_GPREL7_S2, 172)
+ RELOC_NUMBER (R_MICROMIPS_PC23_S2, 173)
+ FAKE_RELOC (R_MICROMIPS_max, 174)
+
/* This was a GNU extension used by embedded-PIC. It was co-opted by
mips-linux for exception-handling data. It is no longer used, but
should continue to be supported by the linker for backward
@@ -147,6 +189,9 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
/* Use MIPS-16 ISA extensions */
#define EF_MIPS_ARCH_ASE_M16 0x04000000
+/* Use MICROMIPS ISA extensions. */
+#define EF_MIPS_ARCH_ASE_MICROMIPS 0x02000000
+
/* Indicates code compiled for a 64-bit machine in 32-bit mode.
(regs are 32-bits wide.) */
#define EF_MIPS_32BITMODE 0x00000100
@@ -733,24 +778,49 @@ extern void bfd_mips_elf32_swap_reginfo_out
#define STO_HIDDEN STV_HIDDEN
#define STO_PROTECTED STV_PROTECTED
+/* Two topmost bits denote the MIPS ISA for .text symbols:
+ + 00 -- standard MIPS code,
+ + 10 -- microMIPS code,
+ + 11 -- MIPS16 code; requires the following two bits to be set too.
+ Note that one of the MIPS16 bits overlaps with STO_MIPS_PIC. See below
+ for details. */
+#define STO_MIPS_ISA (3 << 6)
+
+/* The mask spanning the rest of MIPS psABI flags. At most one is expected
+ to be set except for STO_MIPS16. */
+#define STO_MIPS_FLAGS (~(STO_MIPS_ISA | ELF_ST_VISIBILITY (-1)))
+
/* The MIPS psABI was updated in 2008 with support for PLTs and copy
relocs. There are therefore two types of nonzero SHN_UNDEF functions:
PLT entries and traditional MIPS lazy binding stubs. We mark the former
with STO_MIPS_PLT to distinguish them from the latter. */
#define STO_MIPS_PLT 0x8
+#define ELF_ST_IS_MIPS_PLT(other) (((other) & STO_MIPS_FLAGS) == STO_MIPS_PLT)
+#define ELF_ST_SET_MIPS_PLT(other) (((other) & ~STO_MIPS_FLAGS) | STO_MIPS_PLT)
/* This value is used to mark PIC functions in an object that mixes
- PIC and non-PIC. */
+ PIC and non-PIC. Note that this bit overlaps with STO_MIPS16,
+ although MIPS16 symbols are never considered to be MIPS_PIC. */
#define STO_MIPS_PIC 0x20
-#define ELF_ST_IS_MIPS_PIC(OTHER) \
- (((OTHER) & ~ELF_ST_VISIBILITY (-1)) == STO_MIPS_PIC)
-#define ELF_ST_SET_MIPS_PIC(OTHER) \
- (STO_MIPS_PIC | ELF_ST_VISIBILITY (OTHER))
+#define ELF_ST_IS_MIPS_PIC(other) (((other) & STO_MIPS_FLAGS) == STO_MIPS_PIC)
+#define ELF_ST_SET_MIPS_PIC(other) (((other) & ~STO_MIPS_FLAGS) | STO_MIPS_PIC)
/* This value is used for a mips16 .text symbol. */
#define STO_MIPS16 0xf0
-#define ELF_ST_IS_MIPS16(OTHER) (((OTHER) & 0xf0) == STO_MIPS16)
-#define ELF_ST_SET_MIPS16(OTHER) (((OTHER) & ~0xf0) | STO_MIPS16)
+#define ELF_ST_IS_MIPS16(other) (((other) & STO_MIPS16) == STO_MIPS16)
+#define ELF_ST_SET_MIPS16(other) ((other) | STO_MIPS16)
+
+/* This value is used for a microMIPS .text symbol. To distinguish from
+ STO_MIPS16, we set top two bits to be 10 to denote STO_MICROMIPS. The
+ mask is STO_MIPS_ISA. */
+#define STO_MICROMIPS (2 << 6)
+#define ELF_ST_IS_MICROMIPS(other) (((other) & STO_MIPS_ISA) == STO_MICROMIPS)
+#define ELF_ST_SET_MICROMIPS(other) (((other) & ~STO_MIPS_ISA) | STO_MICROMIPS)
+
+/* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
+ has been indicated for a .text symbol. */
+#define ELF_ST_IS_COMPRESSED(other) \
+ (ELF_ST_IS_MIPS16 (other) || ELF_ST_IS_MICROMIPS (other))
/* This bit is used on Irix to indicate a symbol whose definition
is optional - if, at final link time, it cannot be found, no
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 7f4cdab..3c69275 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,147 @@
+2011-07-24 Chao-ying Fu <fu@mips.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
+ (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
+ (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
+ (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
+ (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
+ (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
+ (OP_MASK_RS3, OP_SH_RS3): Likewise.
+ (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
+ (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
+ (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
+ (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
+ (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
+ (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
+ (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
+ (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
+ (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
+ (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
+ (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
+ (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
+ (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
+ (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
+ (INSN_WRITE_GPR_S): New macro.
+ (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
+ (INSN2_READ_FPR_D): Likewise.
+ (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
+ (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
+ (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
+ (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
+ (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
+ (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
+ (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
+ (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
+ (CPU_MICROMIPS): New macro.
+ (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
+ (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
+ (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
+ (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
+ (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
+ (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
+ (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
+ (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
+ (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
+ (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
+ (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
+ (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
+ (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
+ (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
+ (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
+ (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
+ (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
+ (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
+ (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
+ (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
+ (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
+ (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
+ (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
+ (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
+ (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
+ (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
+ (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
+ (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
+ (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
+ (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
+ (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
+ (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
+ (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
+ (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
+ (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
+ (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
+ (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
+ (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
+ (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
+ (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
+ (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
+ (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
+ (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
+ (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
+ (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
+ (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
+ (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
+ (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
+ (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
+ (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
+ (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
+ (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
+ (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
+ (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
+ (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
+ (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
+ (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
+ (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
+ (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
+ (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
+ (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
+ (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
+ (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
+ (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
+ (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
+ (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
+ (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
+ (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
+ (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
+ (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
+ (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
+ (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
+ (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
+ (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
+ (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
+ (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
+ (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
+ (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
+ (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
+ (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
+ (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
+ (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
+ (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
+ (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
+ (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
+ (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
+ (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
+ (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
+ (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
+ (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
+ (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
+ (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
+ (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
+ (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
+ (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
+ (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
+ (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
+ (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
+ (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
+ (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
+ (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
+ (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
+ (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
+ (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
+ (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
+ (micromips_opcodes): New declaration.
+ (bfd_micromips_num_opcodes): Likewise.
+
2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (INSN_TRAP): Rename to...
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 72a478c..ba68331 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -91,6 +91,10 @@
#define OP_SH_CODE20 6
#define OP_MASK_SHAMT 0x1f
#define OP_SH_SHAMT 6
+#define OP_MASK_EXTLSB OP_MASK_SHAMT
+#define OP_SH_EXTLSB OP_SH_SHAMT
+#define OP_MASK_STYPE OP_MASK_SHAMT
+#define OP_SH_STYPE OP_SH_SHAMT
#define OP_MASK_FD 0x1f
#define OP_SH_FD 6
#define OP_MASK_TARGET 0x3ffffff
@@ -238,6 +242,86 @@
#define OP_SH_FZ 0
#define OP_MASK_FZ 0x1f
+/* Every MICROMIPSOP_X definition requires a corresponding OP_X
+ definition, and vice versa. This simplifies various parts
+ of the operand handling in GAS. The fields below only exist
+ in the microMIPS encoding, so define each one to have an empty
+ range. */
+#define OP_MASK_CODE10 0
+#define OP_SH_CODE10 0
+#define OP_MASK_TRAP 0
+#define OP_SH_TRAP 0
+#define OP_MASK_OFFSET12 0
+#define OP_SH_OFFSET12 0
+#define OP_MASK_OFFSET10 0
+#define OP_SH_OFFSET10 0
+#define OP_MASK_RS3 0
+#define OP_SH_RS3 0
+#define OP_MASK_MB 0
+#define OP_SH_MB 0
+#define OP_MASK_MC 0
+#define OP_SH_MC 0
+#define OP_MASK_MD 0
+#define OP_SH_MD 0
+#define OP_MASK_ME 0
+#define OP_SH_ME 0
+#define OP_MASK_MF 0
+#define OP_SH_MF 0
+#define OP_MASK_MG 0
+#define OP_SH_MG 0
+#define OP_MASK_MH 0
+#define OP_SH_MH 0
+#define OP_MASK_MI 0
+#define OP_SH_MI 0
+#define OP_MASK_MJ 0
+#define OP_SH_MJ 0
+#define OP_MASK_ML 0
+#define OP_SH_ML 0
+#define OP_MASK_MM 0
+#define OP_SH_MM 0
+#define OP_MASK_MN 0
+#define OP_SH_MN 0
+#define OP_MASK_MP 0
+#define OP_SH_MP 0
+#define OP_MASK_MQ 0
+#define OP_SH_MQ 0
+#define OP_MASK_IMMA 0
+#define OP_SH_IMMA 0
+#define OP_MASK_IMMB 0
+#define OP_SH_IMMB 0
+#define OP_MASK_IMMC 0
+#define OP_SH_IMMC 0
+#define OP_MASK_IMMF 0
+#define OP_SH_IMMF 0
+#define OP_MASK_IMMG 0
+#define OP_SH_IMMG 0
+#define OP_MASK_IMMH 0
+#define OP_SH_IMMH 0
+#define OP_MASK_IMMI 0
+#define OP_SH_IMMI 0
+#define OP_MASK_IMMJ 0
+#define OP_SH_IMMJ 0
+#define OP_MASK_IMML 0
+#define OP_SH_IMML 0
+#define OP_MASK_IMMM 0
+#define OP_SH_IMMM 0
+#define OP_MASK_IMMN 0
+#define OP_SH_IMMN 0
+#define OP_MASK_IMMO 0
+#define OP_SH_IMMO 0
+#define OP_MASK_IMMP 0
+#define OP_SH_IMMP 0
+#define OP_MASK_IMMQ 0
+#define OP_SH_IMMQ 0
+#define OP_MASK_IMMU 0
+#define OP_SH_IMMU 0
+#define OP_MASK_IMMW 0
+#define OP_SH_IMMW 0
+#define OP_MASK_IMMX 0
+#define OP_SH_IMMX 0
+#define OP_MASK_IMMY 0
+#define OP_SH_IMMY 0
+
/* This structure holds information for a particular instruction. */
struct mips_opcode
@@ -305,7 +389,8 @@ struct mips_opcode
"z" must be zero register
"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
"+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
- LSB (OP_*_SHAMT).
+ LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for
+ microMIPS compatibility).
Enforces: 0 <= pos < 32.
"+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
Requires that "+A" or "+E" occur first to set position.
@@ -533,6 +618,51 @@ struct mips_opcode
#define INSN2_READ_GPR_D 0x00000200
+/* Instruction has a branch delay slot that requires a 16-bit instruction. */
+#define INSN2_BRANCH_DELAY_16BIT 0x00000400
+/* Instruction has a branch delay slot that requires a 32-bit instruction. */
+#define INSN2_BRANCH_DELAY_32BIT 0x00000800
+/* Modifies the general purpose register in MICROMIPSOP_*_RS. */
+#define INSN2_WRITE_GPR_S 0x00001000
+/* Reads the floating point register in MICROMIPSOP_*_FD. */
+#define INSN2_READ_FPR_D 0x00002000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MB. */
+#define INSN2_MOD_GPR_MB 0x00004000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MC. */
+#define INSN2_MOD_GPR_MC 0x00008000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MD. */
+#define INSN2_MOD_GPR_MD 0x00010000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_ME. */
+#define INSN2_MOD_GPR_ME 0x00020000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MF. */
+#define INSN2_MOD_GPR_MF 0x00040000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MG. */
+#define INSN2_MOD_GPR_MG 0x00080000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MJ. */
+#define INSN2_MOD_GPR_MJ 0x00100000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MP. */
+#define INSN2_MOD_GPR_MP 0x00200000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MQ. */
+#define INSN2_MOD_GPR_MQ 0x00400000
+/* Reads/Writes the stack pointer ($29). */
+#define INSN2_MOD_SP 0x00800000
+/* Reads the RA ($31) register. */
+#define INSN2_READ_GPR_31 0x01000000
+/* Reads the global pointer ($28). */
+#define INSN2_READ_GP 0x02000000
+/* Reads the program counter ($pc). */
+#define INSN2_READ_PC 0x04000000
+/* Is an unconditional branch insn. */
+#define INSN2_UNCOND_BRANCH 0x08000000
+/* Is a conditional branch insn. */
+#define INSN2_COND_BRANCH 0x10000000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MH/I. */
+#define INSN2_MOD_GPR_MHI 0x20000000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MM. */
+#define INSN2_MOD_GPR_MM 0x40000000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MN. */
+#define INSN2_MOD_GPR_MN 0x80000000
+
/* Masks used to mark instructions to indicate which MIPS ISA level
they were introduced in. INSN_ISA_MASK masks an enumeration that
specifies the base ISA level(s). The remainder of a 32-bit
@@ -734,8 +864,13 @@ enum
M_ADDU_I,
M_AND_I,
M_BALIGN,
+ M_BC1FL,
+ M_BC1TL,
+ M_BC2FL,
+ M_BC2TL,
M_BEQ,
M_BEQ_I,
+ M_BEQL,
M_BEQL_I,
M_BGE,
M_BGEL,
@@ -745,6 +880,9 @@ enum
M_BGEUL,
M_BGEU_I,
M_BGEUL_I,
+ M_BGEZ,
+ M_BGEZL,
+ M_BGEZALL,
M_BGT,
M_BGTL,
M_BGT_I,
@@ -753,6 +891,8 @@ enum
M_BGTUL,
M_BGTU_I,
M_BGTUL_I,
+ M_BGTZ,
+ M_BGTZL,
M_BLE,
M_BLEL,
M_BLE_I,
@@ -761,6 +901,8 @@ enum
M_BLEUL,
M_BLEU_I,
M_BLEUL_I,
+ M_BLEZ,
+ M_BLEZL,
M_BLT,
M_BLTL,
M_BLT_I,
@@ -769,10 +911,15 @@ enum
M_BLTUL,
M_BLTU_I,
M_BLTUL_I,
+ M_BLTZ,
+ M_BLTZL,
+ M_BLTZALL,
M_BNE,
+ M_BNEL,
M_BNE_I,
M_BNEL_I,
M_CACHE_AB,
+ M_CACHE_OB,
M_DABS,
M_DADD_I,
M_DADDU_I,
@@ -806,6 +953,9 @@ enum
M_JAL_1,
M_JAL_2,
M_JAL_A,
+ M_JALS_1,
+ M_JALS_2,
+ M_JALS_A,
M_L_DOB,
M_L_DAB,
M_LA_AB,
@@ -819,9 +969,16 @@ enum
M_LD_AB,
M_LDC1_AB,
M_LDC2_AB,
+ M_LDC2_OB,
M_LDC3_AB,
M_LDL_AB,
+ M_LDL_OB,
+ M_LDM_AB,
+ M_LDM_OB,
+ M_LDP_AB,
+ M_LDP_OB,
M_LDR_AB,
+ M_LDR_OB,
M_LH_A,
M_LH_AB,
M_LHU_A,
@@ -832,7 +989,9 @@ enum
M_LI_S,
M_LI_SS,
M_LL_AB,
+ M_LL_OB,
M_LLD_AB,
+ M_LLD_OB,
M_LS_A,
M_LW_A,
M_LW_AB,
@@ -842,13 +1001,21 @@ enum
M_LWC1_AB,
M_LWC2_A,
M_LWC2_AB,
+ M_LWC2_OB,
M_LWC3_A,
M_LWC3_AB,
M_LWL_A,
M_LWL_AB,
+ M_LWL_OB,
+ M_LWM_AB,
+ M_LWM_OB,
+ M_LWP_AB,
+ M_LWP_OB,
M_LWR_A,
M_LWR_AB,
+ M_LWR_OB,
M_LWU_AB,
+ M_LWU_OB,
M_MSGSND,
M_MSGLD,
M_MSGLD_T,
@@ -864,6 +1031,7 @@ enum
M_NOR_I,
M_OR_I,
M_PREF_AB,
+ M_PREF_OB,
M_REM_3,
M_REM_3I,
M_REMU_3,
@@ -881,15 +1049,24 @@ enum
M_S_DAB,
M_S_S,
M_SC_AB,
+ M_SC_OB,
M_SCD_AB,
+ M_SCD_OB,
M_SD_A,
M_SD_OB,
M_SD_AB,
M_SDC1_AB,
M_SDC2_AB,
+ M_SDC2_OB,
M_SDC3_AB,
M_SDL_AB,
+ M_SDL_OB,
+ M_SDM_AB,
+ M_SDM_OB,
+ M_SDP_AB,
+ M_SDP_OB,
M_SDR_AB,
+ M_SDR_OB,
M_SEQ,
M_SEQ_I,
M_SGE,
@@ -920,12 +1097,19 @@ enum
M_SWC1_AB,
M_SWC2_A,
M_SWC2_AB,
+ M_SWC2_OB,
M_SWC3_A,
M_SWC3_AB,
M_SWL_A,
M_SWL_AB,
+ M_SWL_OB,
+ M_SWM_AB,
+ M_SWM_OB,
+ M_SWP_AB,
+ M_SWP_OB,
M_SWR_A,
M_SWR_AB,
+ M_SWR_OB,
M_SUB_I,
M_SUBU_I,
M_SUBU_I_2,
@@ -1145,6 +1329,377 @@ extern int bfd_mips_num_opcodes;
extern const struct mips_opcode mips16_opcodes[];
extern const int bfd_mips16_num_opcodes;
+/* These are the bitmasks and shift counts used for the different
+ fields in the instruction formats. Other than MAJOR, no masks are
+ provided for the fixed portions of an instruction, since they are
+ not needed. */
+
+#define MICROMIPSOP_MASK_MAJOR 0x3f
+#define MICROMIPSOP_SH_MAJOR 26
+#define MICROMIPSOP_MASK_IMMEDIATE 0xffff
+#define MICROMIPSOP_SH_IMMEDIATE 0
+#define MICROMIPSOP_MASK_DELTA 0xffff
+#define MICROMIPSOP_SH_DELTA 0
+#define MICROMIPSOP_MASK_CODE10 0x3ff
+#define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */
+#define MICROMIPSOP_MASK_TRAP 0xf
+#define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */
+#define MICROMIPSOP_MASK_SHAMT 0x1f
+#define MICROMIPSOP_SH_SHAMT 11
+#define MICROMIPSOP_MASK_TARGET 0x3ffffff
+#define MICROMIPSOP_SH_TARGET 0
+#define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */
+#define MICROMIPSOP_SH_EXTLSB 6
+#define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
+#define MICROMIPSOP_SH_EXTMSBD 11
+#define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */
+#define MICROMIPSOP_SH_INSMSB 11
+#define MICROMIPSOP_MASK_CODE 0x3ff
+#define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */
+#define MICROMIPSOP_MASK_CODE2 0x3ff
+#define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */
+#define MICROMIPSOP_MASK_CACHE 0x1f
+#define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */
+#define MICROMIPSOP_MASK_SEL 0x7
+#define MICROMIPSOP_SH_SEL 11
+#define MICROMIPSOP_MASK_OFFSET12 0xfff
+#define MICROMIPSOP_SH_OFFSET12 0
+#define MICROMIPSOP_MASK_STYPE 0x1f
+#define MICROMIPSOP_SH_STYPE 16
+#define MICROMIPSOP_MASK_OFFSET10 0x3ff
+#define MICROMIPSOP_SH_OFFSET10 6
+#define MICROMIPSOP_MASK_RS 0x1f
+#define MICROMIPSOP_SH_RS 16
+#define MICROMIPSOP_MASK_RT 0x1f
+#define MICROMIPSOP_SH_RT 21
+#define MICROMIPSOP_MASK_RD 0x1f
+#define MICROMIPSOP_SH_RD 11
+#define MICROMIPSOP_MASK_FS 0x1f
+#define MICROMIPSOP_SH_FS 16
+#define MICROMIPSOP_MASK_FT 0x1f
+#define MICROMIPSOP_SH_FT 21
+#define MICROMIPSOP_MASK_FD 0x1f
+#define MICROMIPSOP_SH_FD 11
+#define MICROMIPSOP_MASK_FR 0x1f
+#define MICROMIPSOP_SH_FR 6
+#define MICROMIPSOP_MASK_RS3 0x1f
+#define MICROMIPSOP_SH_RS3 6
+#define MICROMIPSOP_MASK_PREFX 0x1f
+#define MICROMIPSOP_SH_PREFX 11
+#define MICROMIPSOP_MASK_BCC 0x7
+#define MICROMIPSOP_SH_BCC 18
+#define MICROMIPSOP_MASK_CCC 0x7
+#define MICROMIPSOP_SH_CCC 13
+#define MICROMIPSOP_MASK_COPZ 0x7fffff
+#define MICROMIPSOP_SH_COPZ 3
+
+#define MICROMIPSOP_MASK_MB 0x7
+#define MICROMIPSOP_SH_MB 23
+#define MICROMIPSOP_MASK_MC 0x7
+#define MICROMIPSOP_SH_MC 4
+#define MICROMIPSOP_MASK_MD 0x7
+#define MICROMIPSOP_SH_MD 7
+#define MICROMIPSOP_MASK_ME 0x7
+#define MICROMIPSOP_SH_ME 1
+#define MICROMIPSOP_MASK_MF 0x7
+#define MICROMIPSOP_SH_MF 3
+#define MICROMIPSOP_MASK_MG 0x7
+#define MICROMIPSOP_SH_MG 0
+#define MICROMIPSOP_MASK_MH 0x7
+#define MICROMIPSOP_SH_MH 7
+#define MICROMIPSOP_MASK_MI 0x7
+#define MICROMIPSOP_SH_MI 7
+#define MICROMIPSOP_MASK_MJ 0x1f
+#define MICROMIPSOP_SH_MJ 0
+#define MICROMIPSOP_MASK_ML 0x7
+#define MICROMIPSOP_SH_ML 4
+#define MICROMIPSOP_MASK_MM 0x7
+#define MICROMIPSOP_SH_MM 1
+#define MICROMIPSOP_MASK_MN 0x7
+#define MICROMIPSOP_SH_MN 4
+#define MICROMIPSOP_MASK_MP 0x1f
+#define MICROMIPSOP_SH_MP 5
+#define MICROMIPSOP_MASK_MQ 0x7
+#define MICROMIPSOP_SH_MQ 7
+
+#define MICROMIPSOP_MASK_IMMA 0x7f
+#define MICROMIPSOP_SH_IMMA 0
+#define MICROMIPSOP_MASK_IMMB 0x7
+#define MICROMIPSOP_SH_IMMB 1
+#define MICROMIPSOP_MASK_IMMC 0xf
+#define MICROMIPSOP_SH_IMMC 0
+#define MICROMIPSOP_MASK_IMMD 0x3ff
+#define MICROMIPSOP_SH_IMMD 0
+#define MICROMIPSOP_MASK_IMME 0x7f
+#define MICROMIPSOP_SH_IMME 0
+#define MICROMIPSOP_MASK_IMMF 0xf
+#define MICROMIPSOP_SH_IMMF 0
+#define MICROMIPSOP_MASK_IMMG 0xf
+#define MICROMIPSOP_SH_IMMG 0
+#define MICROMIPSOP_MASK_IMMH 0xf
+#define MICROMIPSOP_SH_IMMH 0
+#define MICROMIPSOP_MASK_IMMI 0x7f
+#define MICROMIPSOP_SH_IMMI 0
+#define MICROMIPSOP_MASK_IMMJ 0xf
+#define MICROMIPSOP_SH_IMMJ 0
+#define MICROMIPSOP_MASK_IMML 0xf
+#define MICROMIPSOP_SH_IMML 0
+#define MICROMIPSOP_MASK_IMMM 0x7
+#define MICROMIPSOP_SH_IMMM 1
+#define MICROMIPSOP_MASK_IMMN 0x3
+#define MICROMIPSOP_SH_IMMN 4
+#define MICROMIPSOP_MASK_IMMO 0xf
+#define MICROMIPSOP_SH_IMMO 0
+#define MICROMIPSOP_MASK_IMMP 0x1f
+#define MICROMIPSOP_SH_IMMP 0
+#define MICROMIPSOP_MASK_IMMQ 0x7fffff
+#define MICROMIPSOP_SH_IMMQ 0
+#define MICROMIPSOP_MASK_IMMU 0x1f
+#define MICROMIPSOP_SH_IMMU 0
+#define MICROMIPSOP_MASK_IMMW 0x3f
+#define MICROMIPSOP_SH_IMMW 1
+#define MICROMIPSOP_MASK_IMMX 0xf
+#define MICROMIPSOP_SH_IMMX 1
+#define MICROMIPSOP_MASK_IMMY 0x1ff
+#define MICROMIPSOP_SH_IMMY 1
+
+/* Placeholders for fields that only exist in the traditional 32-bit
+ instruction encoding; see the comment above for details. */
+#define MICROMIPSOP_MASK_CODE20 0
+#define MICROMIPSOP_SH_CODE20 0
+#define MICROMIPSOP_MASK_PERFREG 0
+#define MICROMIPSOP_SH_PERFREG 0
+#define MICROMIPSOP_MASK_CODE19 0
+#define MICROMIPSOP_SH_CODE19 0
+#define MICROMIPSOP_MASK_ALN 0
+#define MICROMIPSOP_SH_ALN 0
+#define MICROMIPSOP_MASK_VECBYTE 0
+#define MICROMIPSOP_SH_VECBYTE 0
+#define MICROMIPSOP_MASK_VECALIGN 0
+#define MICROMIPSOP_SH_VECALIGN 0
+#define MICROMIPSOP_MASK_DSPACC 0
+#define MICROMIPSOP_SH_DSPACC 0
+#define MICROMIPSOP_MASK_DSPACC_S 0
+#define MICROMIPSOP_SH_DSPACC_S 0
+#define MICROMIPSOP_MASK_DSPSFT 0
+#define MICROMIPSOP_SH_DSPSFT 0
+#define MICROMIPSOP_MASK_DSPSFT_7 0
+#define MICROMIPSOP_SH_DSPSFT_7 0
+#define MICROMIPSOP_MASK_SA3 0
+#define MICROMIPSOP_SH_SA3 0
+#define MICROMIPSOP_MASK_SA4 0
+#define MICROMIPSOP_SH_SA4 0
+#define MICROMIPSOP_MASK_IMM8 0
+#define MICROMIPSOP_SH_IMM8 0
+#define MICROMIPSOP_MASK_IMM10 0
+#define MICROMIPSOP_SH_IMM10 0
+#define MICROMIPSOP_MASK_WRDSP 0
+#define MICROMIPSOP_SH_WRDSP 0
+#define MICROMIPSOP_MASK_RDDSP 0
+#define MICROMIPSOP_SH_RDDSP 0
+#define MICROMIPSOP_MASK_BP 0
+#define MICROMIPSOP_SH_BP 0
+#define MICROMIPSOP_MASK_MT_U 0
+#define MICROMIPSOP_SH_MT_U 0
+#define MICROMIPSOP_MASK_MT_H 0
+#define MICROMIPSOP_SH_MT_H 0
+#define MICROMIPSOP_MASK_MTACC_T 0
+#define MICROMIPSOP_SH_MTACC_T 0
+#define MICROMIPSOP_MASK_MTACC_D 0
+#define MICROMIPSOP_SH_MTACC_D 0
+#define MICROMIPSOP_MASK_BBITIND 0
+#define MICROMIPSOP_SH_BBITIND 0
+#define MICROMIPSOP_MASK_CINSPOS 0
+#define MICROMIPSOP_SH_CINSPOS 0
+#define MICROMIPSOP_MASK_CINSLM1 0
+#define MICROMIPSOP_SH_CINSLM1 0
+#define MICROMIPSOP_MASK_SEQI 0
+#define MICROMIPSOP_SH_SEQI 0
+#define MICROMIPSOP_SH_OFFSET_A 0
+#define MICROMIPSOP_MASK_OFFSET_A 0
+#define MICROMIPSOP_SH_OFFSET_B 0
+#define MICROMIPSOP_MASK_OFFSET_B 0
+#define MICROMIPSOP_SH_OFFSET_C 0
+#define MICROMIPSOP_MASK_OFFSET_C 0
+#define MICROMIPSOP_SH_RZ 0
+#define MICROMIPSOP_MASK_RZ 0
+#define MICROMIPSOP_SH_FZ 0
+#define MICROMIPSOP_MASK_FZ 0
+
+/* These are the characters which may appears in the args field of a microMIPS
+ instruction. They appear in the order in which the fields appear
+ when the instruction is used. Commas and parentheses in the args
+ string are ignored when assembling, and written into the output
+ when disassembling.
+
+ The followings are for 16-bit microMIPS instructions.
+
+ "ma" must be $28
+ "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4
+ The same register used as both source and target.
+ "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7
+ "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1
+ The same register used as both source and target.
+ "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
+ "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
+ "mh" MIPS registers 4, 5, 6 (MICROMIPSOP_*_MH) at bit 7
+ "mi" MIPS registers 5, 6, 7, 21, 22 (MICROMIPSOP_*_MI) at bit 7
+ ("mh" and "mi" form a valid 3-bit register pair)
+ "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
+ "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
+ "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
+ "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4
+ "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5
+ "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7
+ "mr" must be program counter
+ "ms" must be $29
+ "mt" must be the same as the previous register
+ "mx" must be the same as the destination register
+ "my" must be $31
+ "mz" must be $0
+
+ "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA)
+ "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB)
+ "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255,
+ 32768, 65535) (MICROMIPSOP_*_IMMC)
+ "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD)
+ "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME)
+ "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF)
+ "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG)
+ "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH)
+ "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI)
+ "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ)
+ "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
+ "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM)
+ "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN)
+ "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
+ "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP)
+ "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU)
+ "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW)
+ "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX)
+ "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY)
+ "mZ" must be zero
+
+ In most cases 32-bit microMIPS instructions use the same characters
+ as MIPS (with ADDIUPC being a notable exception, but there are some
+ others too).
+
+ "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
+ "1" 5-bit sync type (MICROMIPSOP_*_SHAMT)
+ "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
+ ">" shift amount between 32 and 63, stored after subtracting 32
+ (MICROMIPSOP_*_SHAMT)
+ "|" 4-bit trap code (MICROMIPSOP_*_TRAP)
+ "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
+ "a" 26-bit target address (MICROMIPSOP_*_TARGET)
+ "b" 5-bit base register (MICROMIPSOP_*_RS)
+ "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
+ "d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
+ "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
+ "i" 16 bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
+ "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
+ "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
+ "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
+ "o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
+ "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
+ "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2)
+ "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS)
+ "s" 5-bit source register specifier (MICROMIPSOP_*_RS)
+ "t" 5-bit target register (MICROMIPSOP_*_RT)
+ "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE)
+ "v" 5-bit same register used as both source and destination
+ (MICROMIPSOP_*_RS)
+ "w" 5-bit same register used as both target and destination
+ (MICROMIPSOP_*_RT)
+ "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
+ "z" must be zero register
+ "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
+ "B" 8-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
+ "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
+
+ "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
+ LSB (MICROMIPSOP_*_EXTLSB).
+ Enforces: 0 <= pos < 32.
+ "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB).
+ Requires that "+A" or "+E" occur first to set position.
+ Enforces: 0 < (pos+size) <= 32.
+ "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
+ Requires that "+A" or "+E" occur first to set position.
+ Enforces: 0 < (pos+size) <= 32.
+ (Also used by DEXT w/ different limits, but limits for
+ that are checked by the M_DEXT macro.)
+ "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB).
+ Enforces: 32 <= pos < 64.
+ "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB).
+ Requires that "+A" or "+E" occur first to set position.
+ Enforces: 32 < (pos+size) <= 64.
+ "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD).
+ Requires that "+A" or "+E" occur first to set position.
+ Enforces: 32 < (pos+size) <= 64.
+ "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
+ Requires that "+A" or "+E" occur first to set position.
+ Enforces: 32 < (pos+size) <= 64.
+
+ PC-relative addition (ADDIUPC) instruction:
+ "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
+ "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23
+
+ Floating point instructions:
+ "D" 5-bit destination register (MICROMIPSOP_*_FD)
+ "M" 3-bit compare condition code (MICROMIPSOP_*_CCC)
+ "N" 3-bit branch condition code (MICROMIPSOP_*_BCC)
+ "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR)
+ "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS)
+ "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT)
+ "V" 5-bit same register used as floating source and destination or target
+ (MICROMIPSOP_*_FS)
+
+ Coprocessor instructions:
+ "E" 5-bit target register (MICROMIPSOP_*_RT)
+ "G" 5-bit destination register (MICROMIPSOP_*_RD)
+ "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
+ "+D" combined destination register ("G") and sel ("H") for CP0 ops,
+ for pretty-printing in disassembly only
+
+ Macro instructions:
+ "A" general 32 bit expression
+ "I" 32-bit immediate (value placed in imm_expr).
+ "+I" 32-bit immediate (value placed in imm2_expr).
+ "F" 64-bit floating point constant in .rdata
+ "L" 64-bit floating point constant in .lit8
+ "f" 32-bit floating point constant
+ "l" 32-bit floating point constant in .lit4
+
+ Other:
+ "()" parens surrounding optional value
+ "," separates operands
+ "+" start of extension sequence
+ "m" start of microMIPS extension sequence
+
+ Characters used so far, for quick reference when adding more:
+ "1234567890"
+ "<>(),+.|~"
+ "ABCDEFGHI KLMN RST V "
+ "abcd f hijklmnopqrstuvw yz"
+
+ Extension character sequences used so far ("+" followed by the
+ following), for quick reference when adding more:
+ ""
+ ""
+ "ABCDEFGHI"
+ ""
+
+ Extension character sequences used so far ("m" followed by the
+ following), for quick reference when adding more:
+ ""
+ ""
+ " BCDEFGHIJ LMNOPQ U WXYZ"
+ " bcdefghij lmn pq st xyz"
+*/
+
+extern const struct mips_opcode micromips_opcodes[];
+extern const int bfd_micromips_num_opcodes;
+
/* A NOP insn impemented as "or at,at,zero".
Used to implement -mfix-loongson2f. */
#define LOONGSON2F_NOP_INSN 0x00200825