Add Intel Itanium Series 9500 support

bfd/

2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>

	* cpu-ia64-opc.c (ins_cnt6a): New function.
	(ext_cnt6a): Ditto.
	(ins_strd5b): Ditto.
	(ext_strd5b): Ditto.
	(elf64_ia64_operands): Add new operand types.

gas/

2012-09-04  Sergey A. Guriev  <sergey.a.guriev@intel.com>

	* config/tc-ia64.c (reg_symbol): Add a new register.
	(indirect_reg): Ditto.
	(pseudo_func): Add new symbolic constants.
	(operand_match): Add new operand types recognition.
	(operand_insn): Add new register recognition.
	(md_begin): Add new register definition.
	(specify_resource): Add new register recognition.

gas/testsuite/

2012-09-04  Sergey A. Guriev  <sergey.a.guriev@intel.com>

	* gas/testsuite/gas/ia64/psn.d: New file.
	* gas/testsuite/gas/ia64/psn.s: New file.
	* gas/testsuite/gas/ia64/ia64.exp: Add new testcase.
	* gas/testsuite/gas/ia64/opc-i.d: Fixed failing tests.
	* gas/testsuite/gas/ia64/opc-m.d: Ditto.

include/opcode/

2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>

	* ia64.h (ia64_opnd): Add new operand types.

opcodes/

2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>

	* ia64-asmtab.h (completer_index): Extend bitfield to full uint.
	* ia64-gen.c: Promote completer index type to longlong.
	(irf_operand): Add new register recognition.
	(in_iclass_mov_x): Add an entry for the new mov_* instruction type.
	(lookup_specifier): Add new resource recognition.
	(insert_bit_table_ent): Relax abort condition according to the
	changed completer index type.
	(print_dis_table): Fix printf format for completer index.
	* ia64-ic.tbl: Add a new instruction class.
	* ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
	* ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
	* ia64-opc.h: Define short names for new operand types.
	* ia64-raw.tbl: Add new RAW resource for DAHR register.
	* ia64-waw.tbl: Add new WAW resource for DAHR register.
	* ia64-asmtab.c: Regenerate.

2 files changed, 35 insertions, 22 deletions

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index e0b0673..ce5c71d 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,22 +1,26 @@
+2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
+
+	* ia64.h (ia64_opnd): Add new operand types.
+
 2012-08-21  David S. Miller  <davem@davemloft.net>
 
 	* sparc.h (F3F4): New macro.
 
 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
-            Laurent Desnogues  <laurent.desnogues@arm.com>
-            Jim MacArthur  <jim.macarthur@arm.com>
-            Marcus Shawcroft  <marcus.shawcroft@arm.com>
-            Nigel Stephens  <nigel.stephens@arm.com>
-            Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-            Richard Earnshaw  <rearnsha@arm.com>
-            Sofiane Naci  <sofiane.naci@arm.com>
-            Tejas Belagod  <tejas.belagod@arm.com>
-            Yufeng Zhang  <yufeng.zhang@arm.com>
+	    Laurent Desnogues  <laurent.desnogues@arm.com>
+	    Jim MacArthur  <jim.macarthur@arm.com>
+	    Marcus Shawcroft  <marcus.shawcroft@arm.com>
+	    Nigel Stephens  <nigel.stephens@arm.com>
+	    Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+	    Richard Earnshaw  <rearnsha@arm.com>
+	    Sofiane Naci  <sofiane.naci@arm.com>
+	    Tejas Belagod  <tejas.belagod@arm.com>
+	    Yufeng Zhang  <yufeng.zhang@arm.com>
 
 	* aarch64.h: New file.
 
 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
-            Maciej W. Rozycki  <macro@codesourcery.com>
+	    Maciej W. Rozycki  <macro@codesourcery.com>
 
 	* mips.h (mips_opcode): Add the exclusions field.
 	(OPCODE_IS_MEMBER): Remove macro.
@@ -24,8 +28,8 @@
 	(opcode_is_member): Likewise.
 
 2012-07-31  Chao-Ying Fu  <fu@mips.com>
-            Catherine Moore  <clm@codesourcery.com>
-            Maciej W. Rozycki  <macro@codesourcery.com>
+	    Catherine Moore  <clm@codesourcery.com>
+	    Maciej W. Rozycki  <macro@codesourcery.com>
 
 	* mips.h: Document microMIPS DSP ASE usage.
 	(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
@@ -110,7 +114,7 @@
 	(XRELEASE_PREFIX_OPCODE): Likewise.
 
 2011-12-08  Andrew Pinski  <apinski@cavium.com>
-            Adam Nemet  <anemet@caviumnetworks.com>
+	    Adam Nemet  <anemet@caviumnetworks.com>
 
 	* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 	(INSN_OCTEON2): New macro.
@@ -141,7 +145,7 @@
 	F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 
 2011-08-09  Chao-ying Fu  <fu@mips.com>
-            Maciej W. Rozycki  <macro@codesourcery.com>
+	    Maciej W. Rozycki  <macro@codesourcery.com>
 
 	* mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 	(OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
@@ -187,7 +191,7 @@
 	(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 
 2011-07-24  Chao-ying Fu  <fu@mips.com>
-            Maciej W. Rozycki  <macro@codesourcery.com>
+	    Maciej W. Rozycki  <macro@codesourcery.com>
 
 	* mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 	(OP_MASK_STYPE, OP_SH_STYPE): Likewise.
@@ -750,7 +754,7 @@
 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 
 	* mips.h: Define CPU_R14000, CPU_R16000.
-        (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
+	(OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 
 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 
@@ -989,9 +993,9 @@
 	* i386.h: Replace CpuMNI with CpuSSSE3.
 
 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
-            Joseph Myers  <joseph@codesourcery.com>
-            Ian Lance Taylor  <ian@wasabisystems.com>
-            Ben Elliston  <bje@wasabisystems.com>
+	    Joseph Myers  <joseph@codesourcery.com>
+	    Ian Lance Taylor  <ian@wasabisystems.com>
+	    Ben Elliston  <bje@wasabisystems.com>
 
 	* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 
@@ -1034,18 +1038,18 @@
 	* m68k.h (mcf_mask): Define.
 
 2006-05-05  Thiemo Seufer  <ths@mips.com>
-            David Ung  <davidu@mips.com>
+	    David Ung  <davidu@mips.com>
 
 	* mips.h (enum): Add macro M_CACHE_AB.
 
 2006-05-04  Thiemo Seufer  <ths@mips.com>
-            Nigel Stephens  <nigel@mips.com>
+	    Nigel Stephens  <nigel@mips.com>
 	    David Ung  <davidu@mips.com>
 
 	* mips.h: Add INSN_SMARTMIPS define.
 
 2006-04-30  Thiemo Seufer  <ths@mips.com>
-            David Ung  <davidu@mips.com>
+	    David Ung  <davidu@mips.com>
 
 	* mips.h: Defines udi bits and masks.  Add description of
 	characters which may appear in the args field of udi
diff --git a/include/opcode/ia64.h b/include/opcode/ia64.h
index 4285377..433c505 100644
--- a/include/opcode/ia64.h
+++ b/include/opcode/ia64.h
@@ -91,6 +91,7 @@ enum ia64_opnd
     IA64_OPND_R2,	/* second register # */
     IA64_OPND_R3,	/* third register # */
     IA64_OPND_R3_2,	/* third register # (limited to gr0-gr3) */
+    IA64_OPND_DAHR3,	/* dahr reg # ( bits 23-25) */
 
     /* memory operands: */
     IA64_OPND_MR3,	/* memory at addr of third register # */
@@ -105,6 +106,7 @@ enum ia64_opnd
     IA64_OPND_PKR_R3,	/* pkr[reg] */
     IA64_OPND_PMC_R3,	/* pmc[reg] */
     IA64_OPND_PMD_R3,	/* pmd[reg] */
+    IA64_OPND_DAHR_R3,	/* dahr[reg] */
     IA64_OPND_RR_R3,	/* rr[reg] */
 
     /* immediate operands: */
@@ -134,7 +136,9 @@ enum ia64_opnd
     IA64_OPND_IMM9a,	/* signed 9-bit immediate (bits 6-12, 27, 36) */
     IA64_OPND_IMM9b,	/* signed 9-bit immediate (bits 13-19, 27, 36) */
     IA64_OPND_IMM14,	/* signed 14-bit immediate (bits 13-19, 27-32, 36) */
+    IA64_OPND_IMMU16,	/* unsigned 16-bit immediate (bits 6-9, 12-22, 36) */
     IA64_OPND_IMM17,	/* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
+    IA64_OPND_IMMU19,	/* unsigned 19-bit immediate (bits 6-9, 12-25, 36) */
     IA64_OPND_IMMU21,	/* unsigned 21-bit immediate (bits 6-25, 36) */
     IA64_OPND_IMM22,	/* signed 22-bit immediate (bits 13-19, 22-36) */
     IA64_OPND_IMMU24,	/* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
@@ -155,6 +159,9 @@ enum ia64_opnd
     IA64_OPND_TGT64,    /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
     IA64_OPND_LDXMOV,	/* any symbol, generates R_IA64_LDXMOV.  */
 
+    IA64_OPND_CNT6a,	/* 6-bit count  (bits 6-11) */
+    IA64_OPND_STRD5b,	/* 5-bit stride (bits 13-17) */
+
     IA64_OPND_COUNT	/* # of operand types (MUST BE LAST!) */
   };
 
@@ -191,6 +198,7 @@ enum ia64_resource_specifier
   IA64_RS_CR_IRR,
   IA64_RS_CR_LRR,
   IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */
+  IA64_RS_DAHR,
   IA64_RS_DBR,
   IA64_RS_FR,
   IA64_RS_FRb,
@@ -212,6 +220,7 @@ enum ia64_resource_specifier
   IA64_RS_PSR, /* PSR bits */
   IA64_RS_RSE, /* implementation-specific RSE resources */
   IA64_RS_AR_FPSR,
+
 };
 
 enum ia64_rse_resource