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| author | Maciej W. Rozycki <macro@orcam.me.uk> | 2023-06-15 04:45:03 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@orcam.me.uk> | 2023-06-15 04:45:03 +0100 |
| commit | 9cfee3962cfbd19dae5cc0087b43be4b276795e7 (patch) | |
| tree | 5fbeea3d01aff3620582f8ae8bd2d841121a982f /include | |
| parent | 0749c73cf8d5308359a75823b887c8cdf2e1b993 (diff) | |
| download | gdb-9cfee3962cfbd19dae5cc0087b43be4b276795e7.zip gdb-9cfee3962cfbd19dae5cc0087b43be4b276795e7.tar.gz gdb-9cfee3962cfbd19dae5cc0087b43be4b276795e7.tar.bz2 | |
Revert "MIPS: sync oprand char usage between mips and micromips"
This reverts commit 5b207b919483f67311a73dfc1de8897ecfd8e776. It was
applied unapproved.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/mips.h | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index ac4085b..666ddae 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -170,10 +170,6 @@ extern "C" { #define OP_MASK_SA3 0x7 #define OP_SH_SA4 21 #define OP_MASK_SA4 0xf -#define OP_SH_SA5 21 -#define OP_MASK_SA5 0x1f -#define OP_SH_SA5_D 11 -#define OP_MASK_SA5_D 0x1f #define OP_SH_IMM8 16 #define OP_MASK_IMM8 0xff #define OP_SH_IMM10 16 @@ -194,10 +190,6 @@ extern "C" { #define OP_MASK_MTACC_T 0x3 #define OP_SH_MTACC_D 13 #define OP_MASK_MTACC_D 0x3 -#define OP_MASK_MT_RX 0x1f -#define OP_SH_MT_RX 6 -#define OP_MASK_MT_SEL 0x7 /* The sel field of mftr and mttr. */ -#define OP_SH_MT_SEL 0 /* MIPS MCU ASE */ #define OP_MASK_3BITPOS 0x7 @@ -898,7 +890,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) "3" 3 bit unsigned immediate (OP_*_SA3) "4" 4 bit unsigned immediate (OP_*_SA4) "5" 8 bit unsigned immediate (OP_*_IMM8) - "6" 5 bit unsigned immediate (OP_*_SA5) + "6" 5 bit unsigned immediate (OP_*_RS) "7" 2 bit dsp accumulator register (OP_*_DSPACC) "8" 6 bit unsigned immediate (OP_*_WRDSP) "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) @@ -906,16 +898,14 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) ":" 7 bit signed immediate (OP_*_DSPSFT_7) "'" 6 bit unsigned immediate (OP_*_RDDSP) "@" 10 bit signed immediate (OP_*_IMM10) - "^" 5 bit unsigned immediate (OP_*_SA5_D) MT ASE usage: "!" 1 bit usermode flag (OP_*_MT_U) "$" 1 bit load high flag (OP_*_MT_H) "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) - "?" 3-bit MFTR and MTTR sel (OP_SH_MT_SEL) "y" 5 bit control target register (OP_*_RT) - "+t" 5 bit control rx register (OP_*_MT_RX) + "+t" 5 bit coprocessor 0 destination register (OP_*_RT) MCU ASE usage: "~" 12 bit offset (OP_*_OFFSET12) |