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| author | Mary Bennett <mary.bennett682@gmail.com> | 2024-05-30 16:06:57 +0100 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-06-05 18:09:09 +0800 |
| commit | 940da069b48980ce957dd4cc010a9a41e05d1553 (patch) | |
| tree | b259f1aeefe9dcafcb45ee0d8497602aa288b03a /include | |
| parent | f95540d91f4c3df373c0f9e212030154658d7f6f (diff) | |
| download | gdb-940da069b48980ce957dd4cc010a9a41e05d1553.zip gdb-940da069b48980ce957dd4cc010a9a41e05d1553.tar.gz gdb-940da069b48980ce957dd4cc010a9a41e05d1553.tar.bz2 | |
RISC-V: Add support for XCVelw extension in CV32E40P
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett682@gmail.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvelw` instruction
class.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi: Note XCVelw as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/cv-elw-fail.d: New test.
* testsuite/gas/riscv/cv-elw-fail.l: New test.
* testsuite/gas/riscv/cv-elw-fail.s: New test.
* testsuite/gas/riscv/cv-elw-fail-march.d: New test.
* testsuite/gas/riscv/cv-elw-fail-march.l: New test.
* testsuite/gas/riscv/cv-elw-fail-march.s: New test.
* testsuite/gas/riscv/cv-elw-pass.d: New test.
* testsuite/gas/riscv/cv-elw-pass.s: New test.
* testsuite/gas/riscv/march-help.l: Add xcvelw string.
opcodes/ChangeLog:
* riscv-opc.c: (riscv_opcode) Add event load instructions.
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK
instruction opcode macros.
* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XCVELW.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc.h | 3 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index ae14e14..73d8c0c 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2469,6 +2469,9 @@ #define MASK_CV_SUBRN 0xc000707f #define MATCH_CV_SUBURN 0xc000305b #define MASK_CV_SUBURN 0xc000707f +/* Vendor-specific (CORE-V) Xcvelw instructions. */ +#define MATCH_CV_ELW 0x600b +#define MASK_CV_ELW 0x707f /* Vendor-specific (T-Head) XTheadBa instructions. */ #define MATCH_TH_ADDSL 0x0000100b #define MASK_TH_ADDSL 0xf800707f diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 5f516a1..d210e70 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -489,6 +489,7 @@ enum riscv_insn_class INSN_CLASS_H, INSN_CLASS_XCVMAC, INSN_CLASS_XCVALU, + INSN_CLASS_XCVELW, INSN_CLASS_XTHEADBA, INSN_CLASS_XTHEADBB, INSN_CLASS_XTHEADBS, |