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| author | Claudio Bantaloukas <claudio.bantaloukas@arm.com> | 2024-06-07 13:59:02 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@arm.com> | 2024-06-12 14:58:35 +0100 |
| commit | 72476aca8f585a026a54cf71ccdf7bed26db1903 (patch) | |
| tree | 317b329a9873bc5308abd0476d0d5d6d36d6a533 /include | |
| parent | 292b9a302933418abcb8b76b23e83af8028c659a (diff) | |
| download | gdb-72476aca8f585a026a54cf71ccdf7bed26db1903.zip gdb-72476aca8f585a026a54cf71ccdf7bed26db1903.tar.gz gdb-72476aca8f585a026a54cf71ccdf7bed26db1903.tar.bz2 | |
aarch64: add Branch Record Buffer extension instructions
The FEAT_BRBE extension provides two aliases of sys:
- brb iall (Invalidates all Branch records in the Branch Record Buffer)
- brb inj (Injects the Branch Record held in BRBINFINJ_EL1,
BRBSRCINJ_EL1, and BRBTGTINJ_EL1 into the Branch Record Buffer)
This patch adds:
- the feature option "brbe" that must be added for the aliases to be available
- a new operand flag AARCH64_OPND_Rt_IN_SYS_ALIASES that warns in a comment
when Rt is set to the non default value 0b11111 (it is constrained
unpredictable whether the instruction is undefined or behaves as if the Rt
field is set to 0b11111).
- a new operand flag AARCH64_OPND_BRBOP that encodes and decodes Op2 values
from bit 5
- support for the two brb aliases above
See:
- https://developer.arm.com/documentation/ddi0602/2024-03/Base-Instructions/BRB--Branch-Record-Buffer--an-alias-of-SYS-?lang=en
- https://developer.arm.com/documentation/ddi0601/2024-03/AArch64-Instructions/BRB-INJ--Branch-Record-Injection-into-the-Branch-Record-Buffer?lang=en
- https://developer.arm.com/documentation/ddi0601/2024-03/AArch64-Instructions/BRB-IALL--Invalidate-the-Branch-Record-Buffer?lang=en
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 8a21611..c83c0a4 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -238,6 +238,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_FP8, /* LUT instructions. */ AARCH64_FEATURE_LUT, + /* Branch Record Buffer Extension */ + AARCH64_FEATURE_BRBE, AARCH64_NUM_FEATURES }; @@ -625,6 +627,8 @@ enum aarch64_opnd AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ AARCH64_OPND_BARRIER_GCSB, /* Barrier operand for GCSB. */ AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */ + AARCH64_OPND_BRBOP, /* BRB operation IALL or INJ in bit 5. */ + AARCH64_OPND_Rt_IN_SYS_ALIASES, /* Defaulted and omitted Rt used in SYS aliases such as brb. */ AARCH64_OPND_LSE128_Rt, /* LSE128 <Xt1>. */ AARCH64_OPND_LSE128_Rt2, /* LSE128 <Xt2>. */ AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */ @@ -822,7 +826,7 @@ enum aarch64_opnd AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB, /* [<Xn|SP>] or [<Xn|SP>, #<imm>]!. */ AARCH64_OPND_RCPC3_ADDR_POSTIND, /* [<Xn|SP>], #<imm>. */ AARCH64_OPND_RCPC3_ADDR_PREIND_WB, /* [<Xn|SP>, #<imm>]!. */ - AARCH64_OPND_RCPC3_ADDR_OFFSET + AARCH64_OPND_RCPC3_ADDR_OFFSET, }; /* Qualifier constrains an operand. It either specifies a variant of an @@ -1918,6 +1922,7 @@ extern const char *const aarch64_sve_pattern_array[32]; extern const char *const aarch64_sve_prfop_array[16]; extern const char *const aarch64_rprfmop_array[64]; extern const char *const aarch64_sme_vlxn_array[2]; +extern const char *const aarch64_brbop_array[2]; #ifdef __cplusplus } |