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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2023-11-02 12:44:13 +0000 |
|---|---|---|
| committer | srinath <srinath.parvathaneni@arm.com> | 2023-11-02 12:45:08 +0000 |
| commit | 6c0ecdbad70456b22b538d957e93478b14d0e0bc (patch) | |
| tree | b7d30ec3fa1c31cf25b37ad07d1b67f52e886d26 /include | |
| parent | 8cee11caccde36068ba1184f2a65f3c170f5a04c (diff) | |
| download | gdb-6c0ecdbad70456b22b538d957e93478b14d0e0bc.zip gdb-6c0ecdbad70456b22b538d957e93478b14d0e0bc.tar.gz gdb-6c0ecdbad70456b22b538d957e93478b14d0e0bc.tar.bz2 | |
aarch64: Add support for Check Feature Status Extension.
This patch adds support for Check Feature Status Extension (CHK) which
is mandatory from Armv8.0-A. Also this patch supports "chkfeat" instruction
(hint #40).
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 631ecf1..a60965c 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -159,9 +159,10 @@ enum aarch64_feature_bit { AARCH64_FEATURE_CSSC, /* Armv8.9-A processors. */ AARCH64_FEATURE_V8_9A, + /* Check Feature Status Extension. */ + AARCH64_FEATURE_CHK, /* SME2. */ AARCH64_FEATURE_SME2, - DUMMY1, DUMMY2, AARCH64_NUM_FEATURES }; @@ -183,7 +184,8 @@ enum aarch64_feature_bit { #define AARCH64_ARCH_V8A_FEATURES(X) (AARCH64_FEATBIT (X, V8A) \ | AARCH64_FEATBIT (X, FP) \ | AARCH64_FEATBIT (X, RAS) \ - | AARCH64_FEATBIT (X, SIMD)) + | AARCH64_FEATBIT (X, SIMD) \ + | AARCH64_FEATBIT (X, CHK)) #define AARCH64_ARCH_V8_1A_FEATURES(X) (AARCH64_FEATBIT (X, V8_1A) \ | AARCH64_FEATBIT (X, CRC) \ | AARCH64_FEATBIT (X, LSE) \ @@ -386,6 +388,7 @@ enum aarch64_opnd AARCH64_OPND_Rm, /* Integer register as source. */ AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ + AARCH64_OPND_X16, /* Integer register x16 in chkfeat instruction. */ AARCH64_OPND_Rt_LS64, /* Integer register used in LS64 instructions. */ AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */ AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ |